From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 4963C384640E for ; Thu, 25 Apr 2024 01:25:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4963C384640E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4963C384640E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714008316; cv=none; b=LWqLOeXUh0bZQA4c2tMJ9Y4SmopQGZTDh/R25AFA9qvjGCfwSvXJixEcWJbLlpLA6FiSglaDcMIC1zZu3ZqaIr9OuuygI2KlhZzXBJ0xNLxoR0hCoTYwQbSHU4voGE2AdLPzZtLNNKTZv9hPn36iF6BPf+3R3nlS00mJ/A07Tso= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714008316; c=relaxed/simple; bh=k62Q0GiVefrIUD7QmnkTOyLsyLwarFJHmWG9e+IaDIM=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=rPk6coP9fOcoP5V4eXpL7/eOI3ZTU4hzEm3LXlRHotv8bbnOO5JZh2cRdpAHuNQccx4HiX5CPvJVsel0GmDFxG3FZz89Mni2mXHy9LfMfEJuCB2C0l2lCOlObPjnC/0M4eLRG4ANIVzZ7P4KldxA1q8CSQaQXPajKsBxMn26EF0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714008314; x=1745544314; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=k62Q0GiVefrIUD7QmnkTOyLsyLwarFJHmWG9e+IaDIM=; b=ZEkbVrNTcQZOuURg8C2/UeywDOxECb5JP+TUU7AxYNYeTmnqnrni39FT BevfJ3nyzmzZq0LozkRcHy7OMbu6yNRyMw+VmSyGnH6BslBcZEjkxmc0c JGzTKTK+gYNWuB4xL2whFNuQqGCm9D4ZoYX8f4gMg4GFYwbK0051Z+hQD BSHLiR0C5M4FeIc/mDTesAUSr347aeD1aZUd5e/aNrmxIVFi/K1KDfdmN NUOQqGt8438TBJNDNjrvJv5hXkLFhxmClgZdE0wgNqaghzchA7xjymwdo ltUlYaF+k5jxWi1khh0TFumb3ctxq99ZHd0gvBM5rGw5F7o0Wmb2hya84 g==; X-CSE-ConnectionGUID: TTk7NxrYSoCwzyHIx7rZEw== X-CSE-MsgGUID: E/fICayySee1wQ4IIPk42w== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9520925" X-IronPort-AV: E=Sophos;i="6.07,227,1708416000"; d="scan'208";a="9520925" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 18:25:13 -0700 X-CSE-ConnectionGUID: miRWCN4uQ+6+3ET0atb1ww== X-CSE-MsgGUID: 7ST8Vw8ATKilVHwzU7G5Ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,227,1708416000"; d="scan'208";a="48148032" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa002.fm.intel.com with ESMTP; 24 Apr 2024 18:25:10 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9FF1D1005193; Thu, 25 Apr 2024 09:25:09 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll Date: Thu, 25 Apr 2024 09:25:08 +0800 Message-Id: <20240425012508.2079105-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li We missed the existing early clobber for the dest operand of vwsll pattern when resolve the conflict of revert register overlap. Thus add it back to the pattern. Unfortunately, we have no test to cover this part and will improve this after GCC-15 open. The below tests are passed for this patch: * The rv64gcv fully regression test with isl build. gcc/ChangeLog: * config/riscv/vector-crypto.md: Add early clobber to the dest operand of vwsll. Signed-off-by: Pan Li --- gcc/config/riscv/vector-crypto.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md index 8a4888a7653..e474ddf5da7 100755 --- a/gcc/config/riscv/vector-crypto.md +++ b/gcc/config/riscv/vector-crypto.md @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll" (set_attr "mode" "")]) (define_insn "@pred_vwsll_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTI (unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1, vmWc1") -- 2.34.1