From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id AD8B5384642D for ; Thu, 25 Apr 2024 09:25:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AD8B5384642D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AD8B5384642D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714037158; cv=none; b=xyWKoarxsNr4oABcJOdhrD3Vc1vGl0wEugzdn9MEFZsDuvyZ4wtxpfxlRPNHOwW1Q/agq90IeNeKB89YcwLUI6jl+0tWTWTmMlhZxmGQHLe7v5gjhNffD0uBgBbfJAy0B6Gllhs43R3JV0GarJ24ZJgjmx3x6yvcJ1S2p11wUMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714037158; c=relaxed/simple; bh=n3bLHB5zvyZjBQWvVXjUTHbkBGB7shrdDPJvUawtqHY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=IqtiAr6rSivy39xHGyDjyQRTkMgxSKuotYO4m4016XUCk2S/VtsP4anMklD11JNF+grGdoXUbboyg6j36180Wy4OJ31B7ehMPiL2zAV/1mVkPOqu7CA6grxsijLcxBRIvLsb6wqCgSMY/ZQTsV2ypgbA03AQvHKdpo8hBJ7WT9M= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714037156; x=1745573156; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=n3bLHB5zvyZjBQWvVXjUTHbkBGB7shrdDPJvUawtqHY=; b=LJDb/apgRiaPG5AzkgmtpZMOpinPvJKr/toc1xq7NlTqXsLpt8QQUXxP n7Im5OcJ5ck5Pq6diqbmJfqORRkEqRZFw2i/OaEmVZGZruyEMJW+B3tQ0 5FbaWwqmDpdU0g3RhJf87lZaF5jjxVv9rg7zbBMeHJSpCsUVkm1QktbJ9 jQOJd/pE+JvbYKo3d1VvQMno53ONr884cIbdzkJxwAyaWZDFVpKmCbUcL /7bwLAe2F/PzjlYRYbasWCwlCBsaKLGqwZgumQuoUQiOjSZA9jiNGrtKG cbHc3ShwX2M3eoco37Hhgxh83DLcD1q+9an9AVUfCarRQgvHuuAH7jngp w==; X-CSE-ConnectionGUID: rh5TZvhJSmCdb3c8NKev8g== X-CSE-MsgGUID: zT4xvRZPR9SoSdtcv/QiaA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9558572" X-IronPort-AV: E=Sophos;i="6.07,228,1708416000"; d="scan'208";a="9558572" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 02:25:54 -0700 X-CSE-ConnectionGUID: WkC52T99RKe0r5rVJisCrg== X-CSE-MsgGUID: gJOSsBvDQsiqCuHtpL/zUg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,228,1708416000"; d="scan'208";a="25002057" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa009.fm.intel.com with ESMTP; 25 Apr 2024 02:25:51 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 46D4F100512A; Thu, 25 Apr 2024 17:25:50 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, Pan Li , Kito Cheng Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714] Date: Thu, 25 Apr 2024 17:25:47 +0800 Message-Id: <20240425092547.2667263-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li We have one ICE when RVV register overlap is enabled. We reverted this feature as it is in stage 4 and there is no much time to figure a better solution for this. Thus, for now add the related test cases which will trigger ICE when register overlap enabled. This will gate the RVV register overlap support in GCC-15. PR target/114714 gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr114714-1.C: New test. * g++.target/riscv/rvv/base/pr114714-2.C: New test. Signed-off-by: Pan Li Co-Authored-by: Kito Cheng --- .../g++.target/riscv/rvv/base/pr114714-1.C | 85 +++++++++++++++++++ .../g++.target/riscv/rvv/base/pr114714-2.C | 85 +++++++++++++++++++ 2 files changed, 170 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C new file mode 100644 index 00000000000..d3230f7f23e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C @@ -0,0 +1,85 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */ + +typedef int a; +typedef short b; +typedef unsigned c; +template < typename > using e = unsigned; +template < typename > void ab(); +#pragma riscv intrinsic "vector" +template < typename f, int, int ac > struct g { + using i = f; + template < typename m > using j = g< m, 0, ac >; + using k = g< i, 1, ac - 1 >; + using ad = g< i, 1, ac + 1 >; +}; +namespace ae { +struct af { + using h = g< short, 6, 0 < 3 >; +}; +struct ag { + using h = af::h; +}; +} template < typename, int > using ah = ae::ag::h; +template < class ai > using aj = typename ai::i; +template < class i, class ai > using j = typename ai::j< i >; +template < class ai > using ak = j< e< ai >, ai >; +template < class ai > using k = typename ai::k; +template < class ai > using ad = typename ai::ad; +template < a ap > vuint16m1_t ar(g< b, ap, 0 >, b); +template < a ap > vuint16m2_t ar(g< b, ap, 1 >, b); +template < a ap > vuint32m2_t ar(g< c, ap, 1 >, c); +template < a ap > vuint32m4_t ar(g< c, ap, 2 >, c); +template < class ai > using as = decltype(ar(ai(), aj< ai >())); +template < class ai > as< ai > at(ai); +namespace ae { +template < int ap > vuint32m4_t au(g< c, ap, 1 + 1 >, vuint32m2_t l) { + return __riscv_vlmul_ext_v_u32m2_u32m4(l); +} +} template < int ap > vuint32m2_t aw(g< c, ap, 1 >, vuint16m1_t l) { + return __riscv_vzext_vf2_u32m2(l, 0); +} +namespace ae { +vuint32m4_t ax(vuint32m4_t, vuint32m4_t, a); +} +template < class ay, class an > as< ay > az(ay ba, an bc) { + an bb; + return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2); +} +template < class bd > as< bd > be(bd, as< ad< bd > >); +namespace ae { +template < class bh, class bi > void bj(bh bk, bi bl) { + ad< decltype(bk) > bn; + az(bn, bl); +} +} template < int ap, int ac, class bp, class bq > +void br(g< c, ap, ac > bk, bp, bq bl) { + ae::bj(bk, bl); +} +template < class ai > using bs = decltype(at(ai())); +struct bt; +template < int ac = 1 > class bu { +public: + template < typename i > void operator()(i) { + ah< i, ac > d; + bt()(i(), d); + } +}; +struct bt { + template < typename bv, class bf > void operator()(bv, bf bw) { + using bx = bv; + ak< bf > by; + k< bf > bz; + using bq = bs< decltype(by) >; + using bp = bs< decltype(bw) >; + bp cb; + ab< bx >(); + for (;;) { + bp cc; + bq bl = aw(by, be(bz, cc)); + br(by, cb, bl); + } + } +}; +void d() { bu()(b()); } diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C new file mode 100644 index 00000000000..55621e98fee --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C @@ -0,0 +1,85 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */ + +typedef int a; +typedef short b; +typedef unsigned c; +template < typename > using e = unsigned; +template < typename > void ab(); +#pragma riscv intrinsic "vector" +template < typename f, int, int ac > struct g { + using i = f; + template < typename m > using j = g< m, 0, ac >; + using k = g< i, 1, ac - 1 >; + using ad = g< i, 1, ac + 1 >; +}; +namespace ae { +struct af { + using h = g< short, 6, 0 < 3 >; +}; +struct ag { + using h = af::h; +}; +} template < typename, int > using ah = ae::ag::h; +template < class ai > using aj = typename ai::i; +template < class i, class ai > using j = typename ai::j< i >; +template < class ai > using ak = j< e< ai >, ai >; +template < class ai > using k = typename ai::k; +template < class ai > using ad = typename ai::ad; +template < a ap > vuint16mf2_t ar(g< b, ap, 0 >, b); +template < a ap > vuint16m1_t ar(g< b, ap, 1 >, b); +template < a ap > vuint32m1_t ar(g< c, ap, 1 >, c); +template < a ap > vuint32m2_t ar(g< c, ap, 2 >, c); +template < class ai > using as = decltype(ar(ai(), aj< ai >())); +template < class ai > as< ai > at(ai); +namespace ae { +template < int ap > vuint32m2_t au(g< c, ap, 1 + 1 >, vuint32m1_t l) { + return __riscv_vlmul_ext_v_u32m1_u32m2(l); +} +} template < int ap > vuint32m1_t aw(g< c, ap, 1 >, vuint16mf2_t l) { + return __riscv_vzext_vf2_u32m1(l, 0); +} +namespace ae { +vuint32m2_t ax(vuint32m2_t, vuint32m2_t, a); +} +template < class ay, class an > as< ay > az(ay ba, an bc) { + an bb; + return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2); +} +template < class bd > as< bd > be(bd, as< ad< bd > >); +namespace ae { +template < class bh, class bi > void bj(bh bk, bi bl) { + ad< decltype(bk) > bn; + az(bn, bl); +} +} template < int ap, int ac, class bp, class bq > +void br(g< c, ap, ac > bk, bp, bq bl) { + ae::bj(bk, bl); +} +template < class ai > using bs = decltype(at(ai())); +struct bt; +template < int ac = 1 > class bu { +public: + template < typename i > void operator()(i) { + ah< i, ac > d; + bt()(i(), d); + } +}; +struct bt { + template < typename bv, class bf > void operator()(bv, bf bw) { + using bx = bv; + ak< bf > by; + k< bf > bz; + using bq = bs< decltype(by) >; + using bp = bs< decltype(bw) >; + bp cb; + ab< bx >(); + for (;;) { + bp cc; + bq bl = aw(by, be(bz, cc)); + br(by, cb, bl); + } + } +}; +void d() { bu()(b()); } -- 2.34.1