From: Patrick O'Neill <patrick@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com, rguenth@gcc.gnu.org,
Patrick O'Neill <patrick@rivosinc.com>
Subject: [PATCH] RISC-V: Add testcase for pr114734
Date: Tue, 30 Apr 2024 13:36:42 -0700 [thread overview]
Message-ID: <20240430203642.4189814-1-patrick@rivosinc.com> (raw)
gcc/testsuite/ChangeLog:
PR middle-end/114734
* gcc.target/riscv/rvv/autovec/pr114734.c: New test.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Tested on rv64gcv before and after Richard Biener's fix:
4d3a5618de5a949c61605f545f90e81bc0000502
---
.../gcc.target/riscv/rvv/autovec/pr114734.c | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644
index 00000000000..b605d992aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3 -mrvv-vector-bits=zvl } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+ for (int m = 0; m < 18; ++m)
+ f[m] = 3;
+ for (int m = 0; m < 18; m += 1)
+ for (int n = 0; n < 18; n += 3) {
+ a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+ b[n] = f[n] ? -i[m] : 0;
+ }
+ for (long n = 0; n < 8; ++n)
+ z = a[n];
+ if (b[15] != 0)
+ __builtin_abort();
+}
--
2.34.1
next reply other threads:[~2024-04-30 20:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 20:36 Patrick O'Neill [this message]
2024-04-30 22:03 ` Jeff Law
2024-05-02 16:23 ` [Committed] " Patrick O'Neill
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