From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by sourceware.org (Postfix) with ESMTPS id AD89E3858D1E for ; Mon, 6 May 2024 18:27:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AD89E3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=quicinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AD89E3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715020056; cv=none; b=t02qlrgTVwpr0lFEH8t7Ftalb6L+C/xNr7uYoH5xdVlxol2hBSHd6BUEvZoYOAxbsHZsEXUCRtL3WdLHkodt1SBkAcEGJK9pVaPLoRWGk2rbVwSgrk/K6BFCF9/OaXirEd0jtmqzRglBX84VcC1DR8/rgepTBBQ0D1Cz0vaEZDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715020056; c=relaxed/simple; bh=7/bIWBST1cGNzVl8d64p/w7PCDZeCc3AgkFrGAN/6ZU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=atmfTYqA/XoLgdmFv3XQmxlxqksSfMd83X85pDkrQ4RaTEPu4JPP53TnIQ8GMdUYEP8+Em5eeCgoxDVv/xEMVYphsbsxtk8yu9yAeyokzXJwRIE8v1WVHY08HCdscDoFNZygw5dr11HhnWyzYFjiTOmpuBv6NoIKVLtOLOBEDiU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 446EdQBx022154 for ; Mon, 6 May 2024 18:27:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=D1YiCqf IZ0RxT/9CXvdf8tk7iGHYAAdlQ0yBKFZTwGk=; b=mwpQ1zaW7OY+/LN969nJomA p/zkPu3lakr9JXAx6xbW/nlkoDsANGJDRimM66zgkWOCcbVFTaiboLWqXyJVbk8c XOgjIKKN2EkXLDLFnIyRxukmrbjjUMo7uxby9lSZ6QcOMIv1tuLIDSIWjYU/nIlQ O7rYgAJP9gjZSL5m7D0SVPHp7ieiNm9iJ6zRjGdzIfTg3yGy3MRu6czXbHK9VrQP 6xxix313tYFKgXlY/R5zgBEj2jtLy3ldLECNvnoMfIdOCYUtsOCZWy8CHa8v3woG MhuUWou8coyHBnnfJjJbxuLSRjgBKeGDcxtwdkNPX0ljZmizAhew2fitA/duPUw= = Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xy15egh1a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 May 2024 18:27:31 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 446IRU8N013647 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 6 May 2024 18:27:30 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 6 May 2024 11:27:30 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64: Add fcsel to cmov integer and csel to float cmov [PR98477] Date: Mon, 6 May 2024 11:27:16 -0700 Message-ID: <20240506182716.4047970-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WqLVwto12cEoPUqQzMWqDAU4fgbI_eMR X-Proofpoint-ORIG-GUID: WqLVwto12cEoPUqQzMWqDAU4fgbI_eMR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-06_13,2024-05-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 mlxscore=0 malwarescore=0 clxscore=1015 mlxlogscore=984 impostorscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405060132 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch adds an alternative to the integer cmov and one to floating point cmov so we avoid in some more moving PR target/98477 gcc/ChangeLog: * config/aarch64/aarch64.md (*cmov_insn[GPI]): Add 'w' alternative. (*cmov_insn[GPF]): Add 'r' alternative. * config/aarch64/iterators.md (wv): New mode attr. gcc/testsuite/ChangeLog: * gcc.target/aarch64/csel_1.c: New test. * gcc.target/aarch64/fcsel_2.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.md | 13 +++++++---- gcc/config/aarch64/iterators.md | 4 ++++ gcc/testsuite/gcc.target/aarch64/csel_1.c | 27 ++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/fcsel_2.c | 20 ++++++++++++++++ 4 files changed, 59 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/csel_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/fcsel_2.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 2bdd443e71d..a6cedd0f1b8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4404,6 +4404,7 @@ (define_insn "*cmov_insn" [ r , Ui1 , rZ ; csel ] csinc\t%0, %4, zr, %M1 [ r , UsM , UsM ; mov_imm ] mov\t%0, -1 [ r , Ui1 , Ui1 ; mov_imm ] mov\t%0, 1 + [ w , w , w ; fcsel ] fcsel\t%0, %3, %4, %m1 } ) @@ -4464,15 +4465,17 @@ (define_insn "*cmovdi_insn_uxtw" ) (define_insn "*cmov_insn" - [(set (match_operand:GPF 0 "register_operand" "=w") + [(set (match_operand:GPF 0 "register_operand" "=r,w") (if_then_else:GPF (match_operator 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]) - (match_operand:GPF 3 "register_operand" "w") - (match_operand:GPF 4 "register_operand" "w")))] + (match_operand:GPF 3 "register_operand" "r,w") + (match_operand:GPF 4 "register_operand" "r,w")))] "TARGET_FLOAT" - "fcsel\\t%0, %3, %4, %m1" - [(set_attr "type" "fcsel")] + "@ + csel\t%0, %3, %4, %m1 + fcsel\\t%0, %3, %4, %m1" + [(set_attr "type" "fcsel,csel")] ) (define_expand "movcc" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 99cde46f1ba..42303f2ec02 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1147,6 +1147,10 @@ (define_mode_attr e [(CCFP "") (CCFPE "e")]) ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) +;; For cmov template to be used with fscel instruction +(define_mode_attr wv [(QI "s") (HI "s") (SI "s") (DI "d") (SF "s") (DF "d")]) + + ;; The size of access, in bytes. (define_mode_attr ldst_sz [(SI "4") (DI "8")]) ;; Likewise for load/store pair. diff --git a/gcc/testsuite/gcc.target/aarch64/csel_1.c b/gcc/testsuite/gcc.target/aarch64/csel_1.c new file mode 100644 index 00000000000..5848e5be2ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/csel_1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-ssa-phiopt" } */ +/* PR target/98477 */ + +/* We should be able to produce csel followed by a store + and not move between the GPRs and simd registers. */ +/* Note -fno-ssa-phiopt is needed, otherwise the tree level + does the VCE after the cmov which allowed to use the csel + instruction. */ +_Static_assert (sizeof(long long) == sizeof(double)); +void +foo (int a, double *b, long long c, long long d) +{ + double ct; + double dt; + __builtin_memcpy(&ct, &c, sizeof(long long)); + __builtin_memcpy(&dt, &d, sizeof(long long)); + double t = a ? ct : dt; + *b = t; +} + +/* { dg-final { scan-assembler-not "\tfcsel\t" } } */ +/* { dg-final { scan-assembler-times "\tcsel\t" 1 } } */ +/* The store should still happen from the GPRs */ +/* { dg-final { scan-assembler-not "\tstr\td" } } */ +/* { dg-final { scan-assembler-times "\tstr\tx" 1 } } */ +/* { dg-final { scan-assembler-not "\tfmov\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel_2.c b/gcc/testsuite/gcc.target/aarch64/fcsel_2.c new file mode 100644 index 00000000000..309e8cbe37f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fcsel_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/98477 */ + +#define vector16 __attribute__((vector_size(16))) +/* We should be able to produce fscel followed by a store + and not move between the GPRs and simd registers. */ +void +foo (int a, int *b, vector16 int c, vector16 int d) +{ + int t = a ? c[0] : d[0]; + *b = t; +} + +/* { dg-final { scan-assembler-times "\tfcsel\t" 1 } } */ +/* { dg-final { scan-assembler-not "\tcsel\t" } } */ +/* The store should still happen from the simd register */ +/* { dg-final { scan-assembler-times "\tstr\ts" 1 } } */ +/* { dg-final { scan-assembler-not "\tstr\tw" } } */ +/* { dg-final { scan-assembler-not "\tfmov\t" } } */ -- 2.43.0