From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id 0AE953858D20 for ; Wed, 8 May 2024 02:12:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0AE953858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0AE953858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715134375; cv=none; b=FZ3y0w5jIB7RP0faJUnDMvXdlG9uDkNeevEUHX8CEPl7BDVOJo7upzSqNx3IgAXO3ru9+L5c1gNPEH8iRc2MDXN35iTb9zkxTXeOZHQocvFwUk1beh7Z5/mt5aG5D5Q9lhsWho6AYa0lhcU1MVTf2SuzwCGcej5oqyPk93E2U1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715134375; c=relaxed/simple; bh=KTIaY4xE1ctMBWlNHx4NQ5z8ohuN1GWBJ8RsO8W3g4I=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=APlI0eR9j0eJecyQO5QhILa+823oZMaRvmc9q5/gFCvHJRMN7S9egfn/79Pxi9TTxaC0zv3UcLs+8M1DcCP8QyRvTym7ola/E+u35Bj+pQ/XZyLb+nKqcW8ZtUBwOO3fiOeb85513uSxSeswqIG55mA3o4q97kpUfTtEgBuKJkU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715134373; x=1746670373; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=KTIaY4xE1ctMBWlNHx4NQ5z8ohuN1GWBJ8RsO8W3g4I=; b=V6rKYdogSH0odFiFHYHbdfTGaEzxTaKZntMnR1jkqeNbdVe4hUp5scED GpDf+DsGfdKV4F8FC26PGXMv88+sCQJkEsZUu/5JN823hw+/7GKPY41Mc Vxt+5jkTl/guYjtOhcbp9O1EWbXIQBGMubdgq9Cj4O0sMw2idvHNVWWbu O53lg3hPAZQC54QI/3cp1mjkvsXKStg0xONAC03eHGfIsSEdg3xo5sd9F gVPYT1NI8kBNYFgOSDoHcJRw6ZSpAMw4BMk1QsdJcSq1niKRdosadYVyL 6WXg+qo0uIvlmaEArx3b3eNDjLdN17erfBlXGw3bqPifMeh2V9LlpsPw7 g==; X-CSE-ConnectionGUID: 92t7pcfIRuSfD96B27/cGQ== X-CSE-MsgGUID: omUt7/YjRy2gRWNg+cUzBQ== X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="14775406" X-IronPort-AV: E=Sophos;i="6.08,143,1712646000"; d="scan'208";a="14775406" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2024 19:12:52 -0700 X-CSE-ConnectionGUID: 8hs3Ydq3Qc++/wJM10Pu5w== X-CSE-MsgGUID: GwS2zEYtSL+BR+/GQFnJOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,143,1712646000"; d="scan'208";a="29287623" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa008.jf.intel.com with ESMTP; 07 May 2024 19:12:48 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 007391007BB7; Wed, 8 May 2024 10:12:47 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Fix some intrinsics without alignment requirements. Date: Wed, 8 May 2024 10:12:47 +0800 Message-Id: <20240508021247.3610284-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, This patch aims to fix some intrinsics without alignment requirement, but raised runtime error's problem. Bootstrapped and tested on x86_64-linux-gnu, OK for trunk? BRs, Lin gcc/ChangeLog: PR target/84508 * config/i386/emmintrin.h (_mm_load_sd): Remove alignment requirement. (_mm_store_sd): Ditto. (_mm_loadh_pd): Ditto. (_mm_loadl_pd): Ditto. (_mm_storel_pd): Add alignment requirement. * config/i386/xmmintrin.h (_mm_loadh_pi): Remove alignment requirement. (_mm_loadl_pi): Ditto. (_mm_load_ss): Ditto. (_mm_store_ss): Ditto. gcc/testsuite/ChangeLog: PR target/84508 * gcc.target/i386/pr84508-1.c: New test. * gcc.target/i386/pr84508-2.c: Ditto. --- gcc/config/i386/emmintrin.h | 11 ++++++----- gcc/config/i386/xmmintrin.h | 9 +++++---- gcc/testsuite/gcc.target/i386/pr84508-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/i386/pr84508-2.c | 11 +++++++++++ 4 files changed, 33 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr84508-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr84508-2.c diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index 915a5234c38..d7fc1af9687 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -56,6 +56,7 @@ typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); /* Unaligned version of the same types. */ typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); +typedef double double_u __attribute__ ((__may_alias__, __aligned__ (1))); /* Create a selector for use with the SHUFPD instruction. */ #define _MM_SHUFFLE2(fp1,fp0) \ @@ -145,7 +146,7 @@ _mm_load1_pd (double const *__P) extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_load_sd (double const *__P) { - return _mm_set_sd (*__P); + return __extension__ (__m128d){ *(double_u *)__P, 0.0 }; } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -180,7 +181,7 @@ _mm_storeu_pd (double *__P, __m128d __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_store_sd (double *__P, __m128d __A) { - *__P = ((__v2df)__A)[0]; + *(double_u *)__P = ((__v2df)__A)[0] ; } extern __inline double __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -192,7 +193,7 @@ _mm_cvtsd_f64 (__m128d __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_storel_pd (double *__P, __m128d __A) { - _mm_store_sd (__P, __A); + *__P = ((__v2df)__A)[0]; } /* Stores the upper DPFP value. */ @@ -973,13 +974,13 @@ _mm_unpacklo_pd (__m128d __A, __m128d __B) extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_loadh_pd (__m128d __A, double const *__B) { - return (__m128d)__builtin_ia32_loadhpd ((__v2df)__A, __B); + return __extension__ (__m128d) { ((__v2df)__A)[0], *(double_u*)__B }; } extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_loadl_pd (__m128d __A, double const *__B) { - return (__m128d)__builtin_ia32_loadlpd ((__v2df)__A, __B); + return __extension__ (__m128d) { *(double_u*)__B, ((__v2df)__A)[1] }; } extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h index 71b9955b843..9e20f262839 100644 --- a/gcc/config/i386/xmmintrin.h +++ b/gcc/config/i386/xmmintrin.h @@ -73,6 +73,7 @@ typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); /* Unaligned version of the same type. */ typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); +typedef float float_u __attribute__ ((__may_alias__, __aligned__ (1))); /* Internal data types for implementing the intrinsics. */ typedef float __v4sf __attribute__ ((__vector_size__ (16))); @@ -774,7 +775,7 @@ _mm_unpacklo_ps (__m128 __A, __m128 __B) /* Sets the upper two SPFP values with 64-bits of data loaded from P; the lower two values are passed through from A. */ extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm_loadh_pi (__m128 __A, __m64 const *__P) +_mm_loadh_pi (__m128 __A, __m64_u const *__P) { return (__m128) __builtin_ia32_loadhps ((__v4sf)__A, (const __v2sf *)__P); } @@ -803,7 +804,7 @@ _mm_movelh_ps (__m128 __A, __m128 __B) /* Sets the lower two SPFP values with 64-bits of data loaded from P; the upper two values are passed through from A. */ extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) -_mm_loadl_pi (__m128 __A, __m64 const *__P) +_mm_loadl_pi (__m128 __A, __m64_u const *__P) { return (__m128) __builtin_ia32_loadlps ((__v4sf)__A, (const __v2sf *)__P); } @@ -910,7 +911,7 @@ _mm_set_ps1 (float __F) extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_load_ss (float const *__P) { - return _mm_set_ss (*__P); + return __extension__ (__m128) (__v4sf){ *(float_u *)__P, 0.0f, 0.0f, 0.0f }; } /* Create a vector with all four elements equal to *P. */ @@ -966,7 +967,7 @@ _mm_setr_ps (float __Z, float __Y, float __X, float __W) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_store_ss (float *__P, __m128 __A) { - *__P = ((__v4sf)__A)[0]; + *(float_u *)__P = ((__v4sf)__A)[0]; } extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__)) diff --git a/gcc/testsuite/gcc.target/i386/pr84508-1.c b/gcc/testsuite/gcc.target/i386/pr84508-1.c new file mode 100644 index 00000000000..bb3e28d017e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr84508-1.c @@ -0,0 +1,11 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-fsanitize=undefined" } */ +#include + +int main() +{ + unsigned char t[16+1]; + __m128d x = _mm_load_sd((const double *)(t+1)); + _mm_store_sd((double*)(t+1), x); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr84508-2.c b/gcc/testsuite/gcc.target/i386/pr84508-2.c new file mode 100644 index 00000000000..32a8f20a536 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr84508-2.c @@ -0,0 +1,11 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-fsanitize=undefined" } */ +#include + +int main() +{ + unsigned char t[8+1]; + __m128 x = _mm_load_ss((const float *)(t)); + _mm_store_ss((float*)(t), x); + return 0; +} -- 2.31.1