From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Jeff Law <jeffreyalaw@gmail.com>,
Vineet Gupta <vineetg@rivosinc.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case
Date: Wed, 8 May 2024 09:36:33 +0200 [thread overview]
Message-ID: <20240508073636.1896951-1-christoph.muellner@vrull.eu> (raw)
We already optimize a sign-extension of a right-shift by 31 in
<optab>si3_extend. Let's add a test for that (similar to
zero-extend-1.c).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sign-extend-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
new file mode 100644
index 00000000000..e9056ec0d42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+signed long
+foo1 (int i)
+{
+ return i >> 31;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+
+/* { dg-final { scan-assembler-not "srai\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "srliw\t" } } */
--
2.44.0
next reply other threads:[~2024-05-08 7:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 7:36 Christoph Müllner [this message]
2024-05-08 7:36 ` [PATCH v2 2/4] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 Christoph Müllner
2024-05-08 13:40 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 3/4] RISC-V: Add zero_extract support for rv64gc Christoph Müllner
2024-05-08 13:46 ` Jeff Law
2024-05-08 7:36 ` [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 Christoph Müllner
2024-05-08 13:48 ` Jeff Law
2024-05-08 14:05 ` Christoph Müllner
2024-05-08 13:38 ` [PATCH v2 1/4] RISC-V: Add test for sraiw-31 special case Jeff Law
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