From: YunQiang Su <syq@gcc.gnu.org>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH] MIPS: Support constraint 'w' for MSA instruction
Date: Wed, 8 May 2024 19:04:33 +0800 [thread overview]
Message-ID: <20240508110433.1285285-1-syq@gcc.gnu.org> (raw)
Support syntax like:
asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
gcc
* config/mips/constraints.md: Add new constraint 'w'.
gcc/testsuite
* gcc.target/mips/msa-inline-asm.c: New test.
---
gcc/config/mips/constraints.md | 3 +++
gcc/testsuite/gcc.target/mips/msa-inline-asm.c | 9 +++++++++
2 files changed, 12 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/mips/msa-inline-asm.c
diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index a96028dd746..f5c88179038 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -29,6 +29,9 @@ (define_register_constraint "t" "T_REG"
(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
"A floating-point register (if available).")
+(define_register_constraint "w" "ISA_HAS_MSA ? FP_REGS : NO_REGS"
+ "A MIPS SIMD register (if available).")
+
(define_register_constraint "h" "NO_REGS"
"Formerly the @code{hi} register. This constraint is no longer supported.")
diff --git a/gcc/testsuite/gcc.target/mips/msa-inline-asm.c b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c
new file mode 100644
index 00000000000..bdf6816ab3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+double
+f(double a, double b, double c) {
+ asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
+ return a;
+}
+/* { dg-final { scan-assembler "fmadd.d \\\$w0, \\\$w\[0-9\]*, \\\$w\[0-9\]*" } } */
--
2.39.2
reply other threads:[~2024-05-08 11:04 UTC|newest]
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