* [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
@ 2024-05-09 3:05 pan2.li
2024-05-09 9:05 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2024-05-09 3:05 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, Pan Li
From: Pan Li <pan2.li@intel.com>
During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body. Because somehow the value of V type is compiler
time constant, and then the second loop will be considered as
assert (true).
Thus, the ccp4 pass will eliminate these stmt and just return 0.
typedef int16_t V __attribute__((vector_size (128)));
int main ()
{
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}
This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index d73bad4af6f..fae2ae91572 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -2,11 +2,12 @@
/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
-#include <assert.h>
/* This would cause us to emit a vl1r.v for VNx4HImode even when
the hardware vector size vl > 64. */
+extern int16_t test_element (int16_t);
+
typedef int16_t V __attribute__((vector_size (128)));
int main ()
@@ -14,9 +15,10 @@ int main ()
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
+
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
- assert (res[i] == i);
+ test_element (res[i]);
}
/* { dg-final { scan-assembler-not {vl[1248]r.v} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
2024-05-09 3:05 [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization pan2.li
@ 2024-05-09 9:05 ` juzhe.zhong
2024-05-09 10:48 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2024-05-09 9:05 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, pan2.li
[-- Attachment #1: Type: text/plain, Size: 2427 bytes --]
lgtm
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-05-09 11:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
From: Pan Li <pan2.li@intel.com>
During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body. Because somehow the value of V type is compiler
time constant, and then the second loop will be considered as
assert (true).
Thus, the ccp4 pass will eliminate these stmt and just return 0.
typedef int16_t V __attribute__((vector_size (128)));
int main ()
{
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}
This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index d73bad4af6f..fae2ae91572 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -2,11 +2,12 @@
/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
-#include <assert.h>
/* This would cause us to emit a vl1r.v for VNx4HImode even when
the hardware vector size vl > 64. */
+extern int16_t test_element (int16_t);
+
typedef int16_t V __attribute__((vector_size (128)));
int main ()
@@ -14,9 +15,10 @@ int main ()
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
+
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
- assert (res[i] == i);
+ test_element (res[i]);
}
/* { dg-final { scan-assembler-not {vl[1248]r.v} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
2024-05-09 9:05 ` juzhe.zhong
@ 2024-05-09 10:48 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2024-05-09 10:48 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3017 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, May 9, 2024 5:05 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
lgtm
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-05-09 11:05
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@gmail.com>; Pan Li<mailto:pan2.li@intel.com>
Subject: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body. Because somehow the value of V type is compiler
time constant, and then the second loop will be considered as
assert (true).
Thus, the ccp4 pass will eliminate these stmt and just return 0.
typedef int16_t V __attribute__((vector_size (128)));
int main ()
{
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}
This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index d73bad4af6f..fae2ae91572 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -2,11 +2,12 @@
/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>
-#include <assert.h>
/* This would cause us to emit a vl1r.v for VNx4HImode even when
the hardware vector size vl > 64. */
+extern int16_t test_element (int16_t);
+
typedef int16_t V __attribute__((vector_size (128)));
int main ()
@@ -14,9 +15,10 @@ int main ()
V v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;
+
V res = v;
for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
- assert (res[i] == i);
+ test_element (res[i]);
}
/* { dg-final { scan-assembler-not {vl[1248]r.v} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-05-09 3:05 [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization pan2.li
2024-05-09 9:05 ` juzhe.zhong
2024-05-09 10:48 ` Li, Pan2
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