From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id 04DEB38708EA for ; Mon, 13 May 2024 18:49:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 04DEB38708EA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 04DEB38708EA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::436 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715626183; cv=none; b=V+xumTpDkLhjT/OVOevMNbIZEmojfMmbY1LOdOulBZKdJ+TBS+jG+vyUZQCx4kaRGvcPbTXFVqov+i9zzqSq02NFeZ/UamkjPS3yI4BSmbaudIXTAGnxOnw0z1WVYwSgFSqrtJ9TQ8j2w131f5hh7+2mcEhgJf25LsZXECMbYaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715626183; c=relaxed/simple; bh=CYyctd68UH4cP6uX59KyYcmUU44AoAPiesi1ZilZWao=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=pC5WD48pkXup0jOU0aUFSpNC8m6k40dRfJl/Yf19h+nMPkvIaFgUAA+orD3ktlrGma5UwioncnR8EP15k6CzY4OW1gpnYespMIP8wZEKSlPLXETDnk82LQ0W8ZEEFVCjCdlYXSpDN5llbZzu4wqPmFMF7NurdZAF4u9ziM2TxaM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6f490b5c23bso3971352b3a.3 for ; Mon, 13 May 2024 11:49:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1715626179; x=1716230979; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BdSRL7H5pj+Ey53F65xSnQGscfJb15iRIJXiXSkgDU8=; b=KU6/pd0LHc7d9eUGJ++VIiXimiKNpvb4eLOAuVCRx6ro6DcGdGzSxTNBnjluE8haw6 4JJfCkokCWNddAJrQi4riSmDgxp2lURrAHHzuDXoLSqyrlM5Bb1GtZuBk7cr/5Dt9V2X RuISg3EIYgncwqzAnuKDubTF1jdcHd3jDMg2WmTLF4NLOVsgjsw7yEcYMM3H86muDezp LHsRRu/ftdKfvCdKi2IIcx6D9yeNaHGPP0nEs3wZ2cgHP3paYq42ySOzqs1m0nJqrWqx WAcKGaw0N91fzQwHcoLI62epeN67QbSjFvxRjTFEDobkgdNXIDBvQivVpIq9KiAez5oA uBTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715626179; x=1716230979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BdSRL7H5pj+Ey53F65xSnQGscfJb15iRIJXiXSkgDU8=; b=s5eKIeFrUJ/OJlFR18EULQd3KfJLKUc1vEXWDQyjWgUEJhov7u9WlzQRFsgfdAusai TxEEU06b3D6XbRI0R/DTlewFdyBP/wTJ+3befiQcWIGY+qKeDfW2SaD+bszqVsnhYYV7 AIZzA+dD7elb/w32NJV0nBIdN1ySu9dpNkvSrlbcJmHOnINk83UwHCHfce/aetD0eDZP cVZNoalS1L/Gwgjt7r+hoiNw/zonymUXzkpOv23FRPnWMdRsfNZHuA3V2bnwpg/LNVYY G9HSRRJY7rxbFR2MTTugnAHZ9vmjoauk8tcdeFYyaSgYTDrSxeINSmjgNN0/6r+FmZnE 3cQQ== X-Gm-Message-State: AOJu0YwxS3f/X00kxxNeX58gnBWt61j6AtWrZQ7xFSp2Ky8bGycFchO5 FlIRKxQAVhrajsYZ1z9OQ8e0lLaTTdtd09EjZM2aEmffxL/TG6+u+qdaUykbTu7UcKWGhGDJPmQ yn2I= X-Google-Smtp-Source: AGHT+IF30v/qtmGljR4ZIUenq0IZ8enhjwkC3bnH6+49uYrZQYi7K6bgrqiOLIEXTzaoc274L/TY3g== X-Received: by 2002:a05:6a00:2d97:b0:6f3:f447:57de with SMTP id d2e1a72fcca58-6f4e02d37a7mr11973951b3a.19.1715626178459; Mon, 13 May 2024 11:49:38 -0700 (PDT) Received: from vineet-framework.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2a66585sm7944336b3a.10.2024.05.13.11.49.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 11:49:38 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Jeff Law , kito.cheng@gmail.com, Palmer Dabbelt , =?UTF-8?q?Christoph=20M=C3=BCllner?= , Robin Dapp , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH v2 2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] Date: Mon, 13 May 2024 11:49:32 -0700 Message-Id: <20240513184932.662109-3-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513184932.662109-1-vineetg@rivosinc.com> References: <20240513184932.662109-1-vineetg@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: If the constant used for stack offset can be expressed as sum of two S12 values, the constant need not be materialized (in a reg) and instead the two S12 bits can be added to instructions involved with frame pointer. This avoids burning a register and more importantly can often get down to be 2 insn vs. 3. The prev patches to generally avoid LUI based const materialization didn't fix this PR and need this directed fix in funcion prologue/epilogue expansion. This fix doesn't move the neddle for SPEC, at all, but it is still a win considering gcc generates one insn fewer than llvm for the test ;-) gcc-13.1 release | gcc 230823 | | | g6619b3d4c15c | This patch | clang/llvm --------------------------------------------------------------------------------- li t0,-4096 | li t0,-4096 | addi sp,sp,-2048 | addi sp,sp,-2048 addi t0,t0,2016 | addi t0,t0,2032 | add sp,sp,-16 | addi sp,sp,-32 li a4,4096 | add sp,sp,t0 | add a5,sp,a0 | add a1,sp,16 add sp,sp,t0 | addi a5,sp,-2032 | sb zero,0(a5) | add a0,a0,a1 li a5,-4096 | add a0,a5,a0 | addi sp,sp,2032 | sb zero,0(a0) addi a4,a4,-2032 | li t0, 4096 | addi sp,sp,32 | addi sp,sp,2032 add a4,a4,a5 | sb zero,2032(a0) | ret | addi sp,sp,48 addi a5,sp,16 | addi t0,t0,-2032 | | ret add a5,a4,a5 | add sp,sp,t0 | add a0,a5,a0 | ret | li t0,4096 | sd a5,8(sp) | sb zero,2032(a0)| addi t0,t0,-2016 | add sp,sp,t0 | ret | gcc/ChangeLog: PR target/105733 * config/riscv/riscv.h: New macros for with aligned offsets. * config/riscv/riscv.cc (riscv_split_sum_of_two_s12): New function to split a sum of two s12 values into constituents. (riscv_expand_prologue): Handle offset being sum of two S12. (riscv_expand_epilogue): Ditto. * config/riscv/riscv-protos.h (riscv_split_sum_of_two_s12): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr105733.c: New Test. * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Adjust to not expect LUI 4096. * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.cc | 74 +++++++++++++++++-- gcc/config/riscv/riscv.h | 7 ++ gcc/testsuite/gcc.target/riscv/pr105733.c | 15 ++++ .../riscv/rvv/autovec/vls/spill-1.c | 4 +- .../riscv/rvv/autovec/vls/spill-2.c | 4 +- .../riscv/rvv/autovec/vls/spill-3.c | 4 +- .../riscv/rvv/autovec/vls/spill-4.c | 4 +- .../riscv/rvv/autovec/vls/spill-5.c | 4 +- .../riscv/rvv/autovec/vls/spill-6.c | 4 +- .../riscv/rvv/autovec/vls/spill-7.c | 4 +- 11 files changed, 105 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr105733.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 706dc204e643..6da6ae4d041f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -166,6 +166,8 @@ extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); extern bool riscv_reg_frame_related (rtx); +extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *, + HOST_WIDE_INT *); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4067505270e1..4b742489b272 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4063,6 +4063,32 @@ riscv_split_doubleword_move (rtx dest, rtx src) riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); } } + +/* Constant VAL is known to be sum of two S12 constants. Break it into + comprising BASE and OFF. + Numerically S12 is -2048 to 2047, however it uses the more conservative + range -2048 to 2032 as offsets pertain to stack related registers. */ + +void +riscv_split_sum_of_two_s12 (HOST_WIDE_INT val, HOST_WIDE_INT *base, + HOST_WIDE_INT *off) +{ + if (SUM_OF_TWO_S12_N (val)) + { + *base = -2048; + *off = val - (-2048); + } + else if (SUM_OF_TWO_S12_P_ALGN (val)) + { + *base = 2032; + *off = val - 2032; + } + else + { + gcc_unreachable (); + } +} + /* Return the appropriate instructions to move SRC into DEST. Assume that SRC is operand 1 and DEST is operand 0. */ @@ -7852,6 +7878,17 @@ riscv_expand_prologue (void) GEN_INT (-constant_frame)); RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; } + else if (SUM_OF_TWO_S12_ALGN (-constant_frame)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (-constant_frame, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (off)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + } else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-constant_frame)); @@ -8074,14 +8111,26 @@ riscv_expand_epilogue (int style) } else { - if (!SMALL_OPERAND (adjust_offset.to_constant ())) + HOST_WIDE_INT adj_off_value = adjust_offset.to_constant (); + if (SMALL_OPERAND (adj_off_value)) + { + adjust = GEN_INT (adj_off_value); + } + else if (SUM_OF_TWO_S12_ALGN (adj_off_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (adj_off_value, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), - GEN_INT (adjust_offset.to_constant ())); + GEN_INT (adj_off_value)); adjust = RISCV_PROLOGUE_TEMP (Pmode); } - else - adjust = GEN_INT (adjust_offset.to_constant ()); } insn = emit_insn ( @@ -8148,10 +8197,21 @@ riscv_expand_epilogue (int style) /* Get an rtx for STEP1 that we can add to BASE. Skip if adjust equal to zero. */ - if (step1.to_constant () != 0) + HOST_WIDE_INT step1_value = step1.to_constant (); + if (step1_value != 0) { - rtx adjust = GEN_INT (step1.to_constant ()); - if (!SMALL_OPERAND (step1.to_constant ())) + rtx adjust = GEN_INT (step1_value); + if (SUM_OF_TWO_S12_ALGN (step1_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (step1_value, &base, &off); + insn = emit_insn (gen_add3_insn (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (base))); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else if (!SMALL_OPERAND (step1_value)) { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); adjust = RISCV_PROLOGUE_TEMP (Pmode); diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0d27c0d378df..d6b14c4d6205 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -641,6 +641,13 @@ enum reg_class #define SUM_OF_TWO_S12(VALUE) \ (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE)) +/* Variant with first value 8 byte aligned if involving stack regs. */ +#define SUM_OF_TWO_S12_P_ALGN(VALUE) \ + (((VALUE) >= (2032 + 1)) && ((VALUE) <= (2032 * 2))) + +#define SUM_OF_TWO_S12_ALGN(VALUE) \ + (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P_ALGN (VALUE)) + /* If this is a single bit mask, then we can load it with bseti. Special handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ #define SINGLE_BIT_MASK_OPERAND(VALUE) \ diff --git a/gcc/testsuite/gcc.target/riscv/pr105733.c b/gcc/testsuite/gcc.target/riscv/pr105733.c new file mode 100644 index 000000000000..6156c36dc7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr105733.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +#define BUF_SIZE 2064 + +void +foo(unsigned long i) +{ + volatile char buf[BUF_SIZE]; + + buf[i] = 0; +} + +/* { dg-final { scan-assembler-not {li\t[a-x0-9]+,4096} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c index b64c73f34f13..6afcf1db593b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c @@ -129,5 +129,5 @@ spill_12 (int8_t *in, int8_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c index 8fcdca705384..544e8628a27b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c @@ -120,5 +120,5 @@ spill_11 (int16_t *in, int16_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c index ca296ce02d66..4bfeb07e9aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c @@ -111,5 +111,5 @@ spill_10 (int32_t *in, int32_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c index ef61d9a2c0c3..1faf31ffd8e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c index 150135a91103..0c8dccc518e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c @@ -120,5 +120,5 @@ spill_11 (_Float16 *in, _Float16 *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c index c5d2d0194348..8bf53b84d1cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c @@ -111,5 +111,5 @@ spill_10 (float *in, float *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c index 70ca683908db..e3980a295406 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ -- 2.34.1