From: Haochen Jiang <haochen.jiang@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: hongtao.liu@intel.com, ubizjak@gmail.com
Subject: [PATCH 1/2] Adjust generic loop alignment from 16:11:8 to 16 for Intel processors
Date: Wed, 15 May 2024 11:04:28 +0800 [thread overview]
Message-ID: <20240515030429.2575440-2-haochen.jiang@intel.com> (raw)
In-Reply-To: <20240515030429.2575440-1-haochen.jiang@intel.com>
Previously, we use 16:11:8 in generic tune for Intel processors, which
lead to cross cache line issue and result in some random performance
penalty in benchmarks with small loops commit to commit.
After changing to always aligning to 16 bytes, it will somehow solve
the issue.
gcc/ChangeLog:
* config/i386/x86-tune-costs.h (generic_cost): Change from
16:11:8 to 16.
---
gcc/config/i386/x86-tune-costs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 65d7d1f7e42..d3aaaa4b5cc 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -3758,7 +3758,7 @@ struct processor_costs generic_cost = {
generic_memset,
COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
- "16:11:8", /* Loop alignment. */
+ "16", /* Loop alignment. */
"16:11:8", /* Jump alignment. */
"0:0:8", /* Label alignment. */
"16", /* Func alignment. */
--
2.31.1
next prev parent reply other threads:[~2024-05-15 3:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 3:04 [PATCH 0/2] Align tight loops to solve cross cacheline issue Haochen Jiang
2024-05-15 3:04 ` Haochen Jiang [this message]
2024-05-15 3:04 ` [PATCH 2/2] Align tight&hot loop without considering max skipping bytes Haochen Jiang
2024-05-15 3:30 ` [PATCH 0/2] Align tight loops to solve cross cacheline issue Jiang, Haochen
2024-05-20 3:15 ` Hongtao Liu
2024-05-27 1:33 ` Hongtao Liu
2024-05-29 3:30 ` Jiang, Haochen
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