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From: pan2.li@intel.com
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com,
	tamar.christina@arm.com, richard.guenther@gmail.com,
	Pan Li <pan2.li@intel.com>
Subject: [PATCH v1 1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD
Date: Sun, 19 May 2024 14:37:07 +0800	[thread overview]
Message-ID: <20240519063708.1847699-1-pan2.li@intel.com> (raw)

From: Pan Li <pan2.li@intel.com>

This patch would like to support the branchless form for unsigned
SAT_ADD when leverage __builtin_add_overflow.  For example as below:

uint64_t sat_add_u(uint64_t x, uint64_t y)
{
  uint64_t ret;
  uint64_t overflow = __builtin_add_overflow (x, y, &ret);

  return (T)(-overflow) | ret;
}

Before this patch:

uint64_t sat_add_u (uint64_t x, uint64_t y)
{
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;
  __complex__ long unsigned int _6;
  uint64_t _8;

;;   basic block 2, loop depth 0
;;    pred:       ENTRY
  _6 = .ADD_OVERFLOW (x_4(D), y_5(D));
  _1 = REALPART_EXPR <_6>;
  _2 = IMAGPART_EXPR <_6>;
  _3 = -_2;
  _8 = _1 | _3;
  return _8;
;;    succ:       EXIT

}

After this patch:

uint64_t sat_add_u (uint64_t x, uint64_t y)
{
  uint64_t _8;

;;   basic block 2, loop depth 0
;;    pred:       ENTRY
  _8 = .SAT_ADD (x_4(D), y_5(D)); [tail call]
  return _8;
;;    succ:       EXIT

}

The below tests suite are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

	* match.pd: Add SAT_ADD right part 2 for __builtin_add_overflow.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/match.pd | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gcc/match.pd b/gcc/match.pd
index b291e34bbe4..5328e846aff 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3064,6 +3064,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (negate (convert (ne (imagpart (IFN_ADD_OVERFLOW:c @0 @1)) integer_zerop)))
  (if (TYPE_UNSIGNED (type) && integer_types_ternary_match (type, @0, @1))))
 
+(match (usadd_right_part_2 @0 @1)
+ (negate (imagpart (IFN_ADD_OVERFLOW:c @0 @1)))
+ (if (TYPE_UNSIGNED (type) && integer_types_ternary_match (type, @0, @1))))
+
 /* We cannot merge or overload usadd_left_part_1 and usadd_left_part_2
    because the sub part of left_part_2 cannot work with right_part_1.
    For example, left_part_2 pattern focus one .ADD_OVERFLOW but the
-- 
2.34.1


             reply	other threads:[~2024-05-19  6:37 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-19  6:37 pan2.li [this message]
2024-05-19  6:37 ` [PATCH v1 2/2] RISC-V: Add test cases for __builtin_add_overflow " pan2.li
2024-05-21 19:49   ` Jeff Law
2024-05-22 13:15 ` [PATCH v1 1/2] Match: Support __builtin_add_overflow for " Richard Biener
2024-05-22 14:33   ` Li, Pan2

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