From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by sourceware.org (Postfix) with ESMTPS id 6B9FC3858D20 for ; Sun, 19 May 2024 06:37:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6B9FC3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6B9FC3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716100639; cv=none; b=hu/td5o/wwHIR1VMis6pTQ3l+j40MaEILp4lINUf2b24YuG6xtRXi+zB/YReILXTW40K5pqwO6ssGv8LKivFoEpEgxD4PIkPsavXml7nrl2KoDO9DBTBqLSlbqX8eyBhAORO/kg4bk9MVVfdzdj3GI5eXb7YXGyVP44bGPN2h4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716100639; c=relaxed/simple; bh=STwATNpkZVf7L/J2ToJkPAOOEibS+TrP1DUZZfgC2wY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=NOpc2bc6PJznj0fJC55uRdBMBAE1i7uMA/RRXE0OhUXBkcKsJK8U+n9lEalijm2CE5yY420ZbluhhrGAwa8FhHXtMjrpVx1HjlTyiclfOrl514kGNpai8JtOPH6I2T6Keinz6CAYT9AMzVWCiSV8jbxoS0Ts2JISYjiuYv9BeIs= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716100638; x=1747636638; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=STwATNpkZVf7L/J2ToJkPAOOEibS+TrP1DUZZfgC2wY=; b=Y/pATb9YVNn8PlyZ2XTFyJv1N+HtdagmQToP6xMbER/YWgdZfwckpz8P CocnHReNFJIhnBj5A2ciPURXuW5w6/h8AVUmlN18zYq80tmw//51w+l6Z fe1bURuzQbRaRHP9Ngp9s+E3SCwrRNZ3EPdDG0sGJThaHFSpwFtrToH0j b8/uSWhiGtmX8NZ3YK9KOdJDEnsnVGrHDuVb5XH21FLpW7kxc/eqPjyBl By0cz0keGLm+2ZHUouRzHVnKWEQsu6q3O8oVOqKtw6lu1SxIfkeDPr632 R1Eact8YFJF/qnEZpVYXvA+7ng43agMDEqbsZfaUS1sH5PjGuFX1pUWqz g==; X-CSE-ConnectionGUID: jhgGXGHOQnK23QLgiAUgTw== X-CSE-MsgGUID: 0jTvv36LT1qiHedkPuPnlQ== X-IronPort-AV: E=McAfee;i="6600,9927,11076"; a="22914000" X-IronPort-AV: E=Sophos;i="6.08,172,1712646000"; d="scan'208";a="22914000" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2024 23:37:16 -0700 X-CSE-ConnectionGUID: RWvxkK7oTT63xYxojSPKeQ== X-CSE-MsgGUID: uLqYe1vkSti+qgFhZYUxdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,172,1712646000"; d="scan'208";a="32339127" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa010.fm.intel.com with ESMTP; 18 May 2024 23:37:14 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 3A5081007C14; Sun, 19 May 2024 14:37:13 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, tamar.christina@arm.com, richard.guenther@gmail.com, Pan Li Subject: [PATCH v1 1/2] Match: Support __builtin_add_overflow for branchless unsigned SAT_ADD Date: Sun, 19 May 2024 14:37:07 +0800 Message-Id: <20240519063708.1847699-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to support the branchless form for unsigned SAT_ADD when leverage __builtin_add_overflow. For example as below: uint64_t sat_add_u(uint64_t x, uint64_t y) { uint64_t ret; uint64_t overflow = __builtin_add_overflow (x, y, &ret); return (T)(-overflow) | ret; } Before this patch: uint64_t sat_add_u (uint64_t x, uint64_t y) { long unsigned int _1; long unsigned int _2; long unsigned int _3; __complex__ long unsigned int _6; uint64_t _8; ;; basic block 2, loop depth 0 ;; pred: ENTRY _6 = .ADD_OVERFLOW (x_4(D), y_5(D)); _1 = REALPART_EXPR <_6>; _2 = IMAGPART_EXPR <_6>; _3 = -_2; _8 = _1 | _3; return _8; ;; succ: EXIT } After this patch: uint64_t sat_add_u (uint64_t x, uint64_t y) { uint64_t _8; ;; basic block 2, loop depth 0 ;; pred: ENTRY _8 = .SAT_ADD (x_4(D), y_5(D)); [tail call] return _8; ;; succ: EXIT } The below tests suite are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fully regression test. gcc/ChangeLog: * match.pd: Add SAT_ADD right part 2 for __builtin_add_overflow. Signed-off-by: Pan Li --- gcc/match.pd | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/match.pd b/gcc/match.pd index b291e34bbe4..5328e846aff 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -3064,6 +3064,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (negate (convert (ne (imagpart (IFN_ADD_OVERFLOW:c @0 @1)) integer_zerop))) (if (TYPE_UNSIGNED (type) && integer_types_ternary_match (type, @0, @1)))) +(match (usadd_right_part_2 @0 @1) + (negate (imagpart (IFN_ADD_OVERFLOW:c @0 @1))) + (if (TYPE_UNSIGNED (type) && integer_types_ternary_match (type, @0, @1)))) + /* We cannot merge or overload usadd_left_part_1 and usadd_left_part_2 because the sub part of left_part_2 cannot work with right_part_1. For example, left_part_2 pattern focus one .ADD_OVERFLOW but the -- 2.34.1