From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by sourceware.org (Postfix) with ESMTPS id 014203858CDB for ; Sun, 19 May 2024 06:37:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 014203858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 014203858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716100643; cv=none; b=CMF8Hwq+NFqzCzvXo9GE0gSKJ0LCG/5JGZjHtDGcFNZ+tH9u8+reuAp0TMWUEPh3eMYCqLezRHBLWeUyfdAd6JAOMcnUfPr9tZrYBdON+QsmA+RUl/0dgoGaOoPIWOfmMPyKitkLFw3PpJM9pVZ4hbnpemJjkKYcST292Y55nL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716100643; c=relaxed/simple; bh=KyFcFPsqcf1tUhocCdk/4hnasvNJYemugU3UzRL2JGc=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=IUgzKykaZWuVkAuCzLCR9XBCcIC+LiHi7rLOfahng2HPj7SQT3R8l4q2rK74spat50uo1aBAbK8FgndULorbQLRqdR8J9Oi8kAntB+QklwOqfXrt8JOF/nUAQk/k9Qcu64gjNsYb5HKyLG1LUOu4Th93ZKfsynrzXCpatWSV3j8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716100640; x=1747636640; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KyFcFPsqcf1tUhocCdk/4hnasvNJYemugU3UzRL2JGc=; b=k+0I0v1cdttYOMadS0ZX/NY/qCkaMmSHcSLbG3928fLZENYvVxiMvad1 mQnXe6REh5fPw+5mB6j/mKISyb6+E5Iii52OLlVu+8TTZeOJdGXnUrpIA NxxNIPOaN0dUl34FgA8pLufSwgtLCvCOyYTAXPsFoqlih38y7MfzYf90Q 958EARrDOjTc0vIaCAVCVKwcB2JOHVWiB1dwTvaRMLX/UmPhRCLl6VGod ibWCTTbWNQllZ0uLRvCLhCDlvLMP1wriuEHXpbmRp4SgiSnkMkZChkcgw s3gv6T+jU2tiz5+R48OLTqSvofF+mGbdQozm+58hDfbAy41roJI7gTH+W A==; X-CSE-ConnectionGUID: 2TF56UEXQxa3VE1lhjHXlw== X-CSE-MsgGUID: y4vFatZmRu6MgaEuPNw7gQ== X-IronPort-AV: E=McAfee;i="6600,9927,11076"; a="22914007" X-IronPort-AV: E=Sophos;i="6.08,172,1712646000"; d="scan'208";a="22914007" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2024 23:37:19 -0700 X-CSE-ConnectionGUID: RZrszpY2SjOttiCaR6zd0g== X-CSE-MsgGUID: PAM0XidGT3C7aOpaZZUZTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,172,1712646000"; d="scan'208";a="32339129" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa010.fm.intel.com with ESMTP; 18 May 2024 23:37:15 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 565F51007C16; Sun, 19 May 2024 14:37:14 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, tamar.christina@arm.com, richard.guenther@gmail.com, Pan Li Subject: [PATCH v1 2/2] RISC-V: Add test cases for __builtin_add_overflow branchless unsigned SAT_ADD Date: Sun, 19 May 2024 14:37:08 +0800 Message-Id: <20240519063708.1847699-2-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240519063708.1847699-1-pan2.li@intel.com> References: <20240519063708.1847699-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_SHORT,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li After we support branchless __builtin_add_overflow unsigned SAT_ADD from the middle end. Add more tests case to cover the functionarlities. The below test suites are passed. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add __builtin_add_overflow test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test. * gcc.target/riscv/sat_u_add-5.c: New test. * gcc.target/riscv/sat_u_add-6.c: New test. * gcc.target/riscv/sat_u_add-7.c: New test. * gcc.target/riscv/sat_u_add-8.c: New test. * gcc.target/riscv/sat_u_add-run-5.c: New test. * gcc.target/riscv/sat_u_add-run-6.c: New test. * gcc.target/riscv/sat_u_add-run-7.c: New test. * gcc.target/riscv/sat_u_add-run-8.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 19 +++++ .../riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 20 +++++ .../riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 20 +++++ .../riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_add-run-5.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_add-run-6.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_add-run-7.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_add-run-8.c | 75 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_arith.h | 27 +++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-5.c | 19 +++++ gcc/testsuite/gcc.target/riscv/sat_u_add-6.c | 21 ++++++ gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 18 +++++ gcc/testsuite/gcc.target/riscv/sat_u_add-8.c | 17 +++++ .../gcc.target/riscv/sat_u_add-run-5.c | 25 +++++++ .../gcc.target/riscv/sat_u_add-run-6.c | 25 +++++++ .../gcc.target/riscv/sat_u_add-run-7.c | 25 +++++++ .../gcc.target/riscv/sat_u_add-run-8.c | 25 +++++++ 17 files changed, 581 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c new file mode 100644 index 00000000000..47d83b0927d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../../../sat_arith.h" + +/* +** vec_sat_u_add_uint8_t_fmt_2: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_FMT_2(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c new file mode 100644 index 00000000000..b5d612dba21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../../../sat_arith.h" + +/* +** vec_sat_u_add_uint16_t_fmt_2: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_FMT_2(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c new file mode 100644 index 00000000000..2e678852c0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../../../sat_arith.h" + +/* +** vec_sat_u_add_uint32_t_fmt_2: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_FMT_2(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c new file mode 100644 index 00000000000..95f145cfdde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../../../sat_arith.h" + +/* +** vec_sat_u_add_uint64_t_fmt_2: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_FMT_2(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c new file mode 100644 index 00000000000..4201b31eb3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../../../sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_2 + +DEF_VEC_SAT_U_ADD_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c new file mode 100644 index 00000000000..35ec9ea3455 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../../../sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_2 + +DEF_VEC_SAT_U_ADD_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c new file mode 100644 index 00000000000..8b1abdb4ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../../../sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_2 + +DEF_VEC_SAT_U_ADD_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 9, + }, + { + 0, 1, 1, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 9, + }, + { + 0, 1, 2, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 18, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c new file mode 100644 index 00000000000..8c72b567590 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../../../sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_2 + +DEF_VEC_SAT_U_ADD_FMT_2(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 9, + }, + { + 0, 1, 2, 18446744073709551614u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index 2ef9fd825f3..781ac11be3c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -10,6 +10,15 @@ sat_u_add_##T##_fmt_1 (T x, T y) \ return (x + y) | (-(T)((T)(x + y) < x)); \ } +#define DEF_SAT_U_ADD_FMT_2(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_2 (T x, T y) \ +{ \ + T ret; \ + T overflow = __builtin_add_overflow (x, y, &ret); \ + return (T)(-overflow) | ret; \ +} + #define DEF_VEC_SAT_U_ADD_FMT_1(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ @@ -23,9 +32,27 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_ADD_FMT_2(T) \ +void __attribute__((noinline)) \ +vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_add_overflow (x, y, &ret); \ + out[i] = (T)(-overflow) | ret; \ + } \ +} + #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) +#define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \ + vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N) #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-5.c new file mode 100644 index 00000000000..4c73c7f8a21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-5.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint8_t_fmt_2: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_ADD_FMT_2(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-6.c new file mode 100644 index 00000000000..0d64f5631bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint16_t_fmt_2: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_ADD_FMT_2(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c new file mode 100644 index 00000000000..fe9dcd4f806 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint32_t_fmt_2: +** addw\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_ADD_FMT_2(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-8.c new file mode 100644 index 00000000000..ebe2ad7b94b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_add_uint64_t_fmt_2: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_ADD_FMT_2(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c new file mode 100644 index 00000000000..508531c09d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 + +DEF_SAT_U_ADD_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c new file mode 100644 index 00000000000..99b5c3a39f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 + +DEF_SAT_U_ADD_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c new file mode 100644 index 00000000000..13f59548935 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 + +DEF_SAT_U_ADD_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c new file mode 100644 index 00000000000..cdbea7b1b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 + +DEF_SAT_U_ADD_FMT_2(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + +#include "scalar_sat_binary.h" -- 2.34.1