* [PATCH v2 0/2] RISC-V: add option -m(no-)autovec-segment
@ 2024-05-28 23:38 Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 1/2] " Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 2/2] Prevent divide-by-zero Patrick O'Neill
0 siblings, 2 replies; 5+ messages in thread
From: Patrick O'Neill @ 2024-05-28 23:38 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu, Patrick O'Neill
Rebased to squash Edwin's fixup into Greg's patch. Split out the middle-end
change and xfailed the associated testcase so the second patch can land
seperately.
Relying on pre-commit CI for full testing.
Greg McGary (2):
RISC-V: add option -m(no-)autovec-segment
Prevent divide-by-zero
gcc/config/riscv/autovec.md | 4 +-
gcc/config/riscv/riscv-opts.h | 5 ++
gcc/config/riscv/riscv.opt | 4 ++
.../gcc.target/riscv/rvv/autovec/no-segment.c | 61 +++++++++++++++++++
.../autovec/struct/mask_struct_load_noseg-1.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-2.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-3.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-4.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-5.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-6.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-7.c | 6 ++
.../struct/mask_struct_load_noseg_run-1.c | 4 ++
.../struct/mask_struct_load_noseg_run-2.c | 4 ++
.../struct/mask_struct_load_noseg_run-3.c | 4 ++
.../struct/mask_struct_load_noseg_run-4.c | 4 ++
.../struct/mask_struct_load_noseg_run-5.c | 4 ++
.../struct/mask_struct_load_noseg_run-6.c | 4 ++
.../struct/mask_struct_load_noseg_run-7.c | 4 ++
.../struct/mask_struct_store_noseg-1.c | 6 ++
.../struct/mask_struct_store_noseg-2.c | 6 ++
.../struct/mask_struct_store_noseg-3.c | 6 ++
.../struct/mask_struct_store_noseg-4.c | 6 ++
.../struct/mask_struct_store_noseg-5.c | 6 ++
.../struct/mask_struct_store_noseg-6.c | 6 ++
.../struct/mask_struct_store_noseg-7.c | 6 ++
.../struct/mask_struct_store_noseg_run-1.c | 4 ++
.../struct/mask_struct_store_noseg_run-2.c | 4 ++
.../struct/mask_struct_store_noseg_run-3.c | 4 ++
.../struct/mask_struct_store_noseg_run-4.c | 4 ++
.../struct/mask_struct_store_noseg_run-5.c | 4 ++
.../struct/mask_struct_store_noseg_run-6.c | 4 ++
.../struct/mask_struct_store_noseg_run-7.c | 4 ++
.../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++
.../autovec/struct/struct_vect_noseg_run-1.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-10.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-11.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-12.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-13.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-14.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-15.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-16.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-17.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-18.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-2.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-3.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-4.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-5.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-6.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-7.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-8.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-9.c | 4 ++
gcc/tree-vect-stmts.cc | 3 +-
69 files changed, 411 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
--
2.43.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] RISC-V: add option -m(no-)autovec-segment
2024-05-28 23:38 [PATCH v2 0/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
@ 2024-05-28 23:38 ` Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 2/2] Prevent divide-by-zero Patrick O'Neill
1 sibling, 0 replies; 5+ messages in thread
From: Patrick O'Neill @ 2024-05-28 23:38 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu
From: Greg McGary <gkm@rivosinc.com>
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes):
Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
* gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro.
* gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option.
* testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c,
testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests.
Tested-by: Edwin Lu <ewlu@rivosinc.com>
---
Added tested-by on Vineet's recommendation. Please wait for riscv precommit to
finish before committing.
---
gcc/config/riscv/autovec.md | 4 +-
gcc/config/riscv/riscv-opts.h | 5 ++
gcc/config/riscv/riscv.opt | 4 ++
.../gcc.target/riscv/rvv/autovec/no-segment.c | 62 +++++++++++++++++++
.../autovec/struct/mask_struct_load_noseg-1.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-2.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-3.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-4.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-5.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-6.c | 6 ++
.../autovec/struct/mask_struct_load_noseg-7.c | 6 ++
.../struct/mask_struct_load_noseg_run-1.c | 4 ++
.../struct/mask_struct_load_noseg_run-2.c | 4 ++
.../struct/mask_struct_load_noseg_run-3.c | 4 ++
.../struct/mask_struct_load_noseg_run-4.c | 4 ++
.../struct/mask_struct_load_noseg_run-5.c | 4 ++
.../struct/mask_struct_load_noseg_run-6.c | 4 ++
.../struct/mask_struct_load_noseg_run-7.c | 4 ++
.../struct/mask_struct_store_noseg-1.c | 6 ++
.../struct/mask_struct_store_noseg-2.c | 6 ++
.../struct/mask_struct_store_noseg-3.c | 6 ++
.../struct/mask_struct_store_noseg-4.c | 6 ++
.../struct/mask_struct_store_noseg-5.c | 6 ++
.../struct/mask_struct_store_noseg-6.c | 6 ++
.../struct/mask_struct_store_noseg-7.c | 6 ++
.../struct/mask_struct_store_noseg_run-1.c | 4 ++
.../struct/mask_struct_store_noseg_run-2.c | 4 ++
.../struct/mask_struct_store_noseg_run-3.c | 4 ++
.../struct/mask_struct_store_noseg_run-4.c | 4 ++
.../struct/mask_struct_store_noseg_run-5.c | 4 ++
.../struct/mask_struct_store_noseg_run-6.c | 4 ++
.../struct/mask_struct_store_noseg_run-7.c | 4 ++
.../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++
.../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++
.../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++
.../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++
.../autovec/struct/struct_vect_noseg_run-1.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-10.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-11.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-12.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-13.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-14.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-15.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-16.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-17.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-18.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-2.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-3.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-4.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-5.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-6.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-7.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-8.c | 4 ++
.../autovec/struct/struct_vect_noseg_run-9.c | 4 ++
68 files changed, 410 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 87d4171bc89..2a7131de749 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -282,7 +282,7 @@
(match_operand:<VM> 2 "vector_mask_operand")
(match_operand 3 "autovec_length_operand")
(match_operand 4 "const_0_operand")]
- "TARGET_VECTOR"
+ "TARGET_VECTOR_AUTOVEC_SEGMENT"
{
riscv_vector::expand_lanes_load_store (operands, true);
DONE;
@@ -295,7 +295,7 @@
(match_operand:<VM> 2 "vector_mask_operand")
(match_operand 3 "autovec_length_operand")
(match_operand 4 "const_0_operand")]
- "TARGET_VECTOR"
+ "TARGET_VECTOR_AUTOVEC_SEGMENT"
{
riscv_vector::expand_lanes_load_store (operands, false);
DONE;
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1b2dd5757a8..9946092b788 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -160,4 +160,9 @@ enum riscv_tls_type {
TLS_DESCRIPTORS
};
+/* On some microarchitectures, vector segment loads and stores are excessively
+ expensive, so predicate the generation of those instrunctions. */
+#define TARGET_VECTOR_AUTOVEC_SEGMENT \
+ (TARGET_VECTOR && riscv_mautovec_segment)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 87f58332016..b92cd458b74 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -628,3 +628,7 @@ Specify TLS dialect.
mfence-tso
Target Var(TARGET_FENCE_TSO) Init(1)
Specifies whether the fence.tso instruction should be used.
+
+mautovec-segment
+Target Integer Var(riscv_mautovec_segment) Init(1)
+Enable (default) or disable generation of vector segment load/store instructions.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
new file mode 100644
index 00000000000..fd996a27501
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
+/* { xfail *-*-* } */
+
+enum e { c, d };
+enum g { f };
+
+struct h
+{
+ float x, w;
+};
+
+struct k
+{
+ short z, y, i, j;
+};
+
+long r;
+struct h m, p;
+struct k *q;
+
+short
+l (float s)
+{
+ if (s <= 0.0f)
+ return 0;
+
+ if (s >= 5)
+ return 5;
+
+ return s;
+}
+
+struct n
+{
+ enum g colorspace;
+};
+
+struct n o (struct k *s, struct h *t)
+{
+ t->w = s->z;
+}
+
+void
+ClutImageChannel (struct n *s, enum e t)
+{
+
+ while (s)
+ for (; r; r++)
+ {
+ o (q, &p);
+
+ if (t & d)
+ q->y = (&m + q->y)->x;
+
+ if (t)
+ q->z = l ((&m + q->z)->w);
+
+ if (s->colorspace)
+ q++;
+ }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
new file mode 100644
index 00000000000..277761263f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
new file mode 100644
index 00000000000..addeba0033d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
new file mode 100644
index 00000000000..c02cff002f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
new file mode 100644
index 00000000000..7b4be34bcf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
new file mode 100644
index 00000000000..0f999187dd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
new file mode 100644
index 00000000000..5dc550b9206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
new file mode 100644
index 00000000000..761b47e61e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
new file mode 100644
index 00000000000..dc577af816b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
new file mode 100644
index 00000000000..0bb4e599816
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
new file mode 100644
index 00000000000..3d70c0dbca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
new file mode 100644
index 00000000000..ca98fd52cbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
new file mode 100644
index 00000000000..190b95a6669
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
new file mode 100644
index 00000000000..769d709ce50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
new file mode 100644
index 00000000000..bcd31f3229c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
new file mode 100644
index 00000000000..c7415ec86f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
new file mode 100644
index 00000000000..f0abda66ef0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
new file mode 100644
index 00000000000..4331c7bac13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
new file mode 100644
index 00000000000..599fbd78e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
new file mode 100644
index 00000000000..1757b0e27b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
new file mode 100644
index 00000000000..0dea4f3300e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
new file mode 100644
index 00000000000..90b8432fbc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
new file mode 100644
index 00000000000..ec7b3811982
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
new file mode 100644
index 00000000000..ca3b3d77136
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
new file mode 100644
index 00000000000..e4fdea08dd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
new file mode 100644
index 00000000000..7f63d204349
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
new file mode 100644
index 00000000000..df0448dcab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
new file mode 100644
index 00000000000..e6268b36098
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
new file mode 100644
index 00000000000..0fdcb8ba85e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
new file mode 100644
index 00000000000..8d040bd2535
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*16,\s*e8,\s*m1,\s*t[au],\s*m[au]} 8 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
new file mode 100644
index 00000000000..9f533f4ff49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-10.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
new file mode 100644
index 00000000000..2b12ed16822
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-11.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
new file mode 100644
index 00000000000..265e2905653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-12.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
new file mode 100644
index 00000000000..ff134ecbbc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-13.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
new file mode 100644
index 00000000000..06648125073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-14.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
new file mode 100644
index 00000000000..356054bf6a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-15.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
new file mode 100644
index 00000000000..21d36c002d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-16.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
new file mode 100644
index 00000000000..7f9763682a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-17.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
new file mode 100644
index 00000000000..86bdc2ca8d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-18.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
new file mode 100644
index 00000000000..24fc8c745ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*m1,\s*t[au],\s*m[au]} 8 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
new file mode 100644
index 00000000000..16f4fd366e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
new file mode 100644
index 00000000000..1d18033e174
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]} 46 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
new file mode 100644
index 00000000000..d5983ef95ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 17 } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
new file mode 100644
index 00000000000..9b158b9b740
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
new file mode 100644
index 00000000000..d9495e77d7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
new file mode 100644
index 00000000000..5e239e8b934
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-8.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
new file mode 100644
index 00000000000..5248f2a39c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-9.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
new file mode 100644
index 00000000000..2a50b7133be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
new file mode 100644
index 00000000000..887a7f9a6e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
new file mode 100644
index 00000000000..f99db9b8f6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
new file mode 100644
index 00000000000..3c320991a0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
new file mode 100644
index 00000000000..588c728968a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
new file mode 100644
index 00000000000..7d4d1bfc899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
new file mode 100644
index 00000000000..c462a1cb925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
new file mode 100644
index 00000000000..35d0febb029
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
new file mode 100644
index 00000000000..4cedba48683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
new file mode 100644
index 00000000000..2bf1cd6984d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
new file mode 100644
index 00000000000..36772aaf900
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
new file mode 100644
index 00000000000..58201220915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
new file mode 100644
index 00000000000..4ac2c39c4ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
new file mode 100644
index 00000000000..dd90a1771a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
new file mode 100644
index 00000000000..0efbee0db9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
new file mode 100644
index 00000000000..c08d13063f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
new file mode 100644
index 00000000000..404f5d664f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
new file mode 100644
index 00000000000..e14ceb9cbf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-9.c"
--
2.43.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] Prevent divide-by-zero
2024-05-28 23:38 [PATCH v2 0/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 1/2] " Patrick O'Neill
@ 2024-05-28 23:38 ` Patrick O'Neill
2024-05-29 7:20 ` Richard Biener
1 sibling, 1 reply; 5+ messages in thread
From: Patrick O'Neill @ 2024-05-28 23:38 UTC (permalink / raw)
To: gcc-patches; +Cc: gkm, jeffreyalaw, vineetg, ewlu
From: Greg McGary <gkm@rivosinc.com>
gcc/ChangeLog:
* gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
* testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: Remove xfail.
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c | 1 -
gcc/tree-vect-stmts.cc | 3 ++-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
index fd996a27501..79d03612a22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
@@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
-/* { xfail *-*-* } */
enum e { c, d };
enum g { f };
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 4219ad832db..34f5736ba00 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11558,7 +11558,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, &num))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, &num))
{
tree ptype;
new_vtype
--
2.43.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] Prevent divide-by-zero
2024-05-28 23:38 ` [PATCH v2 2/2] Prevent divide-by-zero Patrick O'Neill
@ 2024-05-29 7:20 ` Richard Biener
2024-05-29 18:18 ` Patrick O'Neill
0 siblings, 1 reply; 5+ messages in thread
From: Richard Biener @ 2024-05-29 7:20 UTC (permalink / raw)
To: Patrick O'Neill; +Cc: gcc-patches, gkm, jeffreyalaw, vineetg, ewlu
On Wed, May 29, 2024 at 1:39 AM Patrick O'Neill <patrick@rivosinc.com> wrote:
>
> From: Greg McGary <gkm@rivosinc.com>
>
> gcc/ChangeLog:
> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
> * testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: Remove xfail.
> ---
> gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c | 1 -
> gcc/tree-vect-stmts.cc | 3 ++-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
> index fd996a27501..79d03612a22 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
> @@ -1,6 +1,5 @@
> /* { dg-do compile } */
> /* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
> -/* { xfail *-*-* } */
>
> enum e { c, d };
> enum g { f };
> diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
> index 4219ad832db..34f5736ba00 100644
> --- a/gcc/tree-vect-stmts.cc
> +++ b/gcc/tree-vect-stmts.cc
> @@ -11558,7 +11558,8 @@ vectorizable_load (vec_info *vinfo,
> - (vec_num * j + i) * nunits);
> /* remain should now be > 0 and < nunits. */
^^^
> unsigned num;
> - if (constant_multiple_p (nunits, remain, &num))
> + if (known_gt (remain, 0)
So this shouldn't happen. Do you have a testcase where this triggers?
If < nunits doesn't hold things will also go wrong.
Richard.
> + && constant_multiple_p (nunits, remain, &num))
> {
> tree ptype;
> new_vtype
> --
> 2.43.2
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] Prevent divide-by-zero
2024-05-29 7:20 ` Richard Biener
@ 2024-05-29 18:18 ` Patrick O'Neill
0 siblings, 0 replies; 5+ messages in thread
From: Patrick O'Neill @ 2024-05-29 18:18 UTC (permalink / raw)
To: Richard Biener, gkm; +Cc: gcc-patches, jeffreyalaw, vineetg, ewlu
[-- Attachment #1: Type: text/plain, Size: 5211 bytes --]
On 5/29/24 00:20, Richard Biener wrote:
> On Wed, May 29, 2024 at 1:39 AM Patrick O'Neill<patrick@rivosinc.com> wrote:
>> From: Greg McGary<gkm@rivosinc.com>
>>
>> gcc/ChangeLog:
>> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
>> * testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: Remove xfail.
>> ---
>> gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c | 1 -
>> gcc/tree-vect-stmts.cc | 3 ++-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
>> index fd996a27501..79d03612a22 100644
>> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
>> @@ -1,6 +1,5 @@
>> /* { dg-do compile } */
>> /* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
>> -/* { xfail *-*-* } */
>>
>> enum e { c, d };
>> enum g { f };
>> diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
>> index 4219ad832db..34f5736ba00 100644
>> --- a/gcc/tree-vect-stmts.cc
>> +++ b/gcc/tree-vect-stmts.cc
>> @@ -11558,7 +11558,8 @@ vectorizable_load (vec_info *vinfo,
>> - (vec_num * j + i) * nunits);
>> /* remain should now be > 0 and < nunits. */
> ^^^
>
>> unsigned num;
>> - if (constant_multiple_p (nunits, remain, &num))
>> + if (known_gt (remain, 0)
> So this shouldn't happen. Do you have a testcase where this triggers?
> If < nunits doesn't hold things will also go wrong.
This ICE appears after patch 1 of the series is applied with the testcase:
testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
Executing on host: /home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c -march=rv64gc_zba_zbb_zbc_zbs -mabi=lp64d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment -S -o no-segment.s (timeout = 600)
spawn -ignore SIGHUP /home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c -march=rv64gc_zba_zbb_zbc_zbs -mabi=lp64d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment -S -o no-segment.s
during GIMPLE pass: vect
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: In function 'ClutImageChannel':
/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c:45:1: internal compiler error: Floating point exception
0x13e06b3 crash_signal
../../../gcc/gcc/toplev.cc:319
0x2840977 poly_int<2u, poly_result<unsigned long, unsigned long, poly_coeff_pair_traits<unsigned long, unsigned long>::result_kind>::type> operator-<2u, unsigned long, unsigned long>(poly_int<2u, unsigned long> const&, poly_int<2u, unsigned long> const&)
../../../gcc/gcc/poly-int.h:871
0x2840977 vectorizable_load
../../../gcc/gcc/tree-vect-stmts.cc:11558
0x284da2d vect_transform_stmt(vec_info*, _stmt_vec_info*, gimple_stmt_iterator*, _slp_tree*, _slp_instance*)
../../../gcc/gcc/tree-vect-stmts.cc:13416
0x16a00ce vect_transform_loop_stmt
../../../gcc/gcc/tree-vect-loop.cc:11618
0x16ca4f2 vect_transform_loop(_loop_vec_info*, gimple*)
../../../gcc/gcc/tree-vect-loop.cc:12144
0x1712a8d vect_transform_loops
../../../gcc/gcc/tree-vectorizer.cc:1006
0x17131c3 try_vectorize_loop_1
../../../gcc/gcc/tree-vectorizer.cc:1152
0x17131c3 try_vectorize_loop
../../../gcc/gcc/tree-vectorizer.cc:1182
0x17137fc execute
../../../gcc/gcc/tree-vectorizer.cc:1298
Please submit a full bug report, with preprocessed source (by using -freport-bug).
Please include the complete backtrace with any bug report.
See<https://gcc.gnu.org/bugs/> for instructions.
compiler exited with status 1
Greg created this patch as a fix for that ICE so I'm guessing it was
root-caused to be a nunits == 0 divide-by-zero.
@Greg McGary is the author of this patch and would know best.
Patrick
>
> Richard.
>
>
>> + && constant_multiple_p (nunits, remain, &num))
>> {
>> tree ptype;
>> new_vtype
>> --
>> 2.43.2
>>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-05-29 18:18 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-28 23:38 [PATCH v2 0/2] RISC-V: add option -m(no-)autovec-segment Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 1/2] " Patrick O'Neill
2024-05-28 23:38 ` [PATCH v2 2/2] Prevent divide-by-zero Patrick O'Neill
2024-05-29 7:20 ` Richard Biener
2024-05-29 18:18 ` Patrick O'Neill
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