From: pan2.li@intel.com
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, Pan Li <pan2.li@intel.com>
Subject: [PATCH v1 5/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
Date: Mon, 3 Jun 2024 11:09:53 +0800 [thread overview]
Message-ID: <20240603030953.3333366-5-pan2.li@intel.com> (raw)
In-Reply-To: <20240603030953.3333366-1-pan2.li@intel.com>
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 5 of unsigned .SAT_ADD.
Form 5:
#define SAT_ADD_U_5(T) \
T sat_add_u_5_##T(T x, T y) \
{ \
return (T)(x + y) < x ? -1 : (x + y); \
}
Passed the riscv fully regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test macro for form 5.
* gcc.target/riscv/sat_u_add-21.c: New test.
* gcc.target/riscv/sat_u_add-22.c: New test.
* gcc.target/riscv/sat_u_add-23.c: New test.
* gcc.target/riscv/sat_u_add-24.c: New test.
* gcc.target/riscv/sat_u_add-run-21.c: New test.
* gcc.target/riscv/sat_u_add-run-22.c: New test.
* gcc.target/riscv/sat_u_add-run-23.c: New test.
* gcc.target/riscv/sat_u_add-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_add-21.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_add-22.c | 21 ++++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_add-23.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_add-24.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_add-run-21.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add-run-22.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add-run-23.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add-run-24.c | 25 +++++++++++++++++++
9 files changed, 183 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-24.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 6ca158d57c4..976ef1c44c1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -42,6 +42,13 @@ sat_u_add_##T##_fmt_5 (T x, T y) \
return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \
}
+#define DEF_SAT_U_ADD_FMT_6(T) \
+T __attribute__((noinline)) \
+sat_u_add_##T##_fmt_6 (T x, T y) \
+{ \
+ return (T)(x + y) < x ? -1 : (x + y); \
+}
+
#define DEF_VEC_SAT_U_ADD_FMT_1(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
@@ -60,6 +67,7 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
#define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y)
#define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y)
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
+#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-21.c
new file mode 100644
index 00000000000..f75e35a5fa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-21.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint8_t_fmt_6:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_FMT_6(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-22.c
new file mode 100644
index 00000000000..ad957a061f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-22.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint16_t_fmt_6:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_FMT_6(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c
new file mode 100644
index 00000000000..3b82bdffb59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint32_t_fmt_6:
+** addw\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_FMT_6(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-24.c
new file mode 100644
index 00000000000..6072d69b4dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-24.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint64_t_fmt_6:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_FMT_6(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-21.c
new file mode 100644
index 00000000000..8bc204ec74e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-21.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6
+
+DEF_SAT_U_ADD_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-22.c
new file mode 100644
index 00000000000..d304288d8b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-22.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6
+
+DEF_SAT_U_ADD_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-23.c
new file mode 100644
index 00000000000..1a1ea598133
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-23.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6
+
+DEF_SAT_U_ADD_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-run-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-24.c
new file mode 100644
index 00000000000..dc977d5b3a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-run-24.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6
+
+DEF_SAT_U_ADD_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
next prev parent reply other threads:[~2024-06-03 3:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-03 3:09 [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 pan2.li
2024-06-03 3:09 ` [PATCH v1 2/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 pan2.li
2024-06-03 3:19 ` juzhe.zhong
2024-06-03 3:09 ` [PATCH v1 3/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 pan2.li
2024-06-03 3:19 ` juzhe.zhong
2024-06-03 3:09 ` [PATCH v1 4/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 pan2.li
2024-06-03 3:19 ` juzhe.zhong
2024-06-03 3:09 ` pan2.li [this message]
2024-06-03 3:19 ` [PATCH v1 5/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 juzhe.zhong
2024-06-03 3:18 ` [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 juzhe.zhong
2024-06-03 3:24 ` Li, Pan2
2024-06-07 0:55 ` Li, Pan2
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