From: Patrick O'Neill <patrick@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: jeffreyalaw@gmail.com, kito.cheng@gmail.com,
gnu-toolchain@rivosinc.com,
Patrick O'Neill <patrick@rivosinc.com>
Subject: [PATCH 3/3] RISC-V: Allow any temp register to be used in amo tests
Date: Tue, 11 Jun 2024 11:03:42 -0700 [thread overview]
Message-ID: <20240611180342.2420602-4-patrick@rivosinc.com> (raw)
In-Reply-To: <20240611180342.2420602-1-patrick@rivosinc.com>
We artifically restrict the temp registers to be a[0-9]+ when other
registers like t[0-9]+ are valid too. Update to make the regex
accept any register for the temp value.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex.
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c | 4 ++--
.../gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c | 4 ++--
12 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
index 3c79035e46d..53dd5234452 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
@@ -6,8 +6,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a0\)
-** sw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
index 7d74841846f..dda0f541515 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
@@ -6,9 +6,9 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a0\)
** fence\tr,rw
-** sw\ta[0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
index ab95fa660d2..3279557fa4a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
@@ -7,9 +7,9 @@
/*
** foo:
** fence\trw,rw
-** lw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a0\)
** fence\tr,rw
-** sw\ta[0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
index d852fddf03d..6b05429520b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
@@ -6,8 +6,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
-** sw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
index ccb5e2af7cc..1ad7dede931 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
@@ -6,9 +6,9 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a1\)
** fence\trw,w
-** sw\ta[0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a0\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
index 761889f18cf..b16b2058413 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
@@ -6,9 +6,9 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a1\)
** fence\trw,w
-** sw\ta[0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a0\)
** fence\trw,rw
** ret
*/
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
index 631977985bd..ebb0a2e1d38 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
@@ -7,8 +7,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a0\)
-** sw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
index 2c24f10fb44..c88c4be5aea 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
@@ -7,8 +7,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a0\)
-** sw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
index 7d2166d29c0..8713729c378 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
@@ -8,8 +8,8 @@
/*
** foo:
** fence\trw,rw
-** lw\ta[0-9]+,0\(a0\)
-** sw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
index 29a770285ef..ca8d5ed7515 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
@@ -7,8 +7,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
-** sw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
index fb82360ad33..23957198cfb 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
@@ -7,8 +7,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
-** sw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
** ret
*/
void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
index 88d8432d8c9..11c12f0ca1a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
@@ -7,8 +7,8 @@
/*
** foo:
-** lw\ta[0-9]+,0\(a1\)
-** sw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
** fence\trw,rw
** ret
*/
--
2.34.1
next prev parent reply other threads:[~2024-06-11 18:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-11 18:03 [PATCH 0/3] RISC-V: Amo testsuite cleanup Patrick O'Neill
2024-06-11 18:03 ` [PATCH 1/3] RISC-V: Move amo tests into subfolder Patrick O'Neill
2024-06-11 18:03 ` [PATCH 2/3] RISC-V: Fix amoadd call arguments Patrick O'Neill
2024-06-11 18:03 ` Patrick O'Neill [this message]
2024-06-12 18:12 ` [PATCH 0/3] RISC-V: Amo testsuite cleanup Jeff Law
2024-06-12 18:20 ` [Committed] " Patrick O'Neill
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