From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by sourceware.org (Postfix) with ESMTPS id B4407388211C for ; Fri, 14 Jun 2024 02:13:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B4407388211C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B4407388211C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718331220; cv=none; b=Xixl85YMfIDwV0OlVXusVm9lvarsdAjzsGAkY6z9YlryjB65tk3ys4gmZQEuH3D+b1BybXq1Tm2Gitqlfny98RoN3ev5BZwb8/A/Z0WqmoJWCWNAkDUtGqIKQ5yywUnoz53SEU4x6/YfNfu03NOpululGTLe8O2vY8Rp6MP8WOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718331220; c=relaxed/simple; bh=m9oDhMOkyDMb2VsPNPjjPK95wx9pZwH+PLHz+tY/oVQ=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=FjUPG9q0ZKC/rsOPnNP4uHJdmKZUV5l/vRXiDB1x5ihqpvsU5/PMlTgs3zfphlQa75ySh5rSV8iLJYzxIRmP3rGW4NJPvTq2CzL10dMpgQfME177tbwnhZbZL1UDbXOYPFlqHqguI0NQ2ZwrJoqvT2LS4ywN7RkuRbQTD0CCOPM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718331218; x=1749867218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m9oDhMOkyDMb2VsPNPjjPK95wx9pZwH+PLHz+tY/oVQ=; b=L5AaLEjxcxyGwBjsWpjiDGRpH8x7zs/PBx/OZprIYy8TCgVeA45eh0QL Nfi7g8po746cSrqhOLf5B/k5fBpAfOT6Rdw5ECHBy3SwimDmP/Fw7gdD+ zt2ziGyZX1L9KMylmod7/toKqH/d39lGahKi0SWxPOxihy2YgtpUBx+iz JzMIz53Xv2vnkfuO7tsC5pbcjsXV00l08jhJcIIYUdeDM3MffXhrV5L+M JzvGVhHWQIvHexDSDNuQ1Ej6pQtJQz7gAgcSM7tuexzVAO0gZdPmE5hoF yWXtYQSi7Ec9DHVHh39fzC1LQrpr5L52EXM5/vxH7pvA1lk2o8/4NHCvc g==; X-CSE-ConnectionGUID: Tbpt2xYsScWvIw6/o8hFrw== X-CSE-MsgGUID: oU/QWHw/RkatD89eVm1bhw== X-IronPort-AV: E=McAfee;i="6700,10204,11102"; a="15431445" X-IronPort-AV: E=Sophos;i="6.08,236,1712646000"; d="scan'208";a="15431445" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2024 19:13:36 -0700 X-CSE-ConnectionGUID: C8sXkOXDTJ2yKkqHFaZBBA== X-CSE-MsgGUID: pCtn/KJNSxuDF6scwlJ6LQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,236,1712646000"; d="scan'208";a="45481314" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa004.jf.intel.com with ESMTP; 13 Jun 2024 19:13:34 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id BFA0C1007820; Fri, 14 Jun 2024 10:13:32 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 Date: Fri, 14 Jun 2024 10:13:23 +0800 Message-Id: <20240614021328.3032144-3-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240614021328.3032144-1-pan2.li@intel.com> References: <20240614021328.3032144-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 5 of unsigned .SAT_SUB. Form 5: #define SAT_SUB_U_5(T) \ T sat_sub_u_5_##T (T x, T y) \ { \ return x < y ? 0 : x - y; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-17.c: New test. * gcc.target/riscv/sat_u_sub-18.c: New test. * gcc.target/riscv/sat_u_sub-19.c: New test. * gcc.target/riscv/sat_u_sub-20.c: New test. * gcc.target/riscv/sat_u_sub-run-17.c: New test. * gcc.target/riscv/sat_u_sub-run-18.c: New test. * gcc.target/riscv/sat_u_sub-run-19.c: New test. * gcc.target/riscv/sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c | 19 ++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c | 17 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-17.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-18.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-19.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-20.c | 25 +++++++++++++++++++ 9 files changed, 180 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index b2f8478d36b..d08755dd861 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -106,10 +106,18 @@ sat_u_sub_##T##_fmt_4 (T x, T y) \ return x >= y ? x - y : 0; \ } +#define DEF_SAT_U_SUB_FMT_5(T) \ +T __attribute__((noinline)) \ +sat_u_sub_##T##_fmt_5 (T x, T y) \ +{ \ + return x < y ? 0 : x - y; \ +} + #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y) #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y) #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y) #define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y) +#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y) #define DEF_VEC_SAT_U_SUB_FMT_1(T) \ void __attribute__((noinline)) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c new file mode 100644 index 00000000000..853ddcfd285 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint8_t_fmt_5: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_SUB_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c new file mode 100644 index 00000000000..423a6f82170 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint16_t_fmt_5: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_SUB_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c new file mode 100644 index 00000000000..29b9c235d97 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint32_t_fmt_5: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_SUB_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c new file mode 100644 index 00000000000..89e84d60f94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint64_t_fmt_5: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+a0,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_SUB_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c new file mode 100644 index 00000000000..b2823112b62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5 + +DEF_SAT_U_SUB_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 255, 254, 1, }, + { 255, 255, 0, }, + { 254, 255, 0, }, + { 253, 254, 0, }, + { 0, 255, 0, }, + { 1, 255, 0, }, + { 32, 5, 27, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c new file mode 100644 index 00000000000..9f575a47bfe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5 + +DEF_SAT_U_SUB_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 65535, 65534, 1, }, + { 65535, 65535, 0, }, + { 65534, 65535, 0, }, + { 65533, 65534, 0, }, + { 0, 65535, 0, }, + { 1, 65535, 0, }, + { 35, 5, 30, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c new file mode 100644 index 00000000000..c370455c3d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5 + +DEF_SAT_U_SUB_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 4294967295, 4294967294, 1, }, + { 4294967295, 4294967295, 0, }, + { 4294967294, 4294967295, 0, }, + { 4294967293, 4294967294, 0, }, + { 1, 4294967295, 0, }, + { 2, 4294967295, 0, }, + { 5, 1, 4, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c new file mode 100644 index 00000000000..22d82f973d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5 + +DEF_SAT_U_SUB_FMT_5(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 18446744073709551615u, 18446744073709551614u, 1, }, + { 18446744073709551615u, 18446744073709551615u, 0, }, + { 18446744073709551614u, 18446744073709551615u, 0, }, + { 18446744073709551613u, 18446744073709551614u, 0, }, + { 0, 18446744073709551615u, 0, }, + { 1, 18446744073709551615u, 0, }, + { 43, 11, 32, }, +}; + +#include "scalar_sat_binary.h" -- 2.34.1