From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id F15CD387084B for ; Sat, 15 Jun 2024 13:49:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F15CD387084B Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F15CD387084B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718459370; cv=none; b=wH6pOjD/T5ZfHQz3CNq8NmNo+4MlVLWkfolpFQ9p+/3KVcX/mIz2bNOLxsI5/goPOlqJpxVJxQl6HPTGXIBnkcMakSEO7M+7qCsk9ayEwZHRFHU58DBnLOQbS0nb8oQ0Q2TemDnO47XME9MlMjn4hmPCfqWuJp9WOBJCUvS/8Gw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718459370; c=relaxed/simple; bh=FvWPQux+lJe2gT0AgFgqm3kOzldgfLUb4AKy+Yui2fQ=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=jj5aCNh3MKEkiVH0uBvISenvOyyBntCTB7M4gNjzrltBUmc1RrdQSr6wWtokYN3Nt6KmYjw2AOA8eBvROdLTWdQlqAdAiXL83FVWvKHftfc9iaJRZatGqWG6DzzkH4GhKV9iL5YeI4JFTBWP/oVbzHPAjAhU/4x3A40g+8GlcqY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1718459368; bh=FvWPQux+lJe2gT0AgFgqm3kOzldgfLUb4AKy+Yui2fQ=; h=From:To:Cc:Subject:Date:From; b=GhUEVxKr7WLqZdw9MrGKy/MAlN0h0VED/hev+EtDOPcbG0Jx006ZEWkVvhwxb25K9 c5zhdBiHnFC5fQVeDpur82nd5iuHmB31X/DwTNwrddzN8K0sIVc0ttWbMJag4i8XmR pTRWVh3oDv6c2/6+CAeBp/IDGsUi9+Te5xfBroJg= Received: from stargazer.. (unknown [IPv6:240e:457:1130:3532:fcd1:d9f4:2ad1:565c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 5255666A75; Sat, 15 Jun 2024 09:49:20 -0400 (EDT) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH] LoongArch: Only transform move/move/bstrins to srai/bstrins when -Os Date: Sat, 15 Jun 2024 21:47:31 +0800 Message-ID: <20240615134745.14671-1-xry111@xry111.site> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The first form has a lower latency (due to the special handling of "move" in LA464 and LA664) despite it's longer. gcc/ChangeLog: * config/loongarch/loongarch.md (define_peephole2): Require optimize_insn_for_size_p () for move/move/bstrins => srai/bstrins transform. --- Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? gcc/config/loongarch/loongarch.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 25c1d323ba0..e4434c3bd4e 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1617,20 +1617,23 @@ (define_insn_and_split "*bstrins__for_ior_mask" }) ;; We always avoid the shift operation in bstrins__for_ior_mask -;; if possible, but the result may be sub-optimal when one of the masks +;; if possible, but the result may be larger when one of the masks ;; is (1 << N) - 1 and one of the src register is the dest register. ;; For example: ;; move t0, a0 ;; move a0, a1 ;; bstrins.d a0, t0, 42, 0 ;; ret -;; using a shift operation would be better: +;; using a shift operation would be smaller: ;; srai.d t0, a1, 43 ;; bstrins.d a0, t0, 63, 43 ;; ret ;; unfortunately we cannot figure it out in split1: before reload we cannot ;; know if the dest register is one of the src register. Fix it up in ;; peephole2. +;; +;; Note that the first form has a lower latency so this should only be +;; done when optimizing for size. (define_peephole2 [(set (match_operand:GPR 0 "register_operand") (match_operand:GPR 1 "register_operand")) @@ -1639,7 +1642,7 @@ (define_peephole2 (match_operand:SI 3 "const_int_operand") (const_int 0)) (match_dup 0))] - "peep2_reg_dead_p (3, operands[0])" + "peep2_reg_dead_p (3, operands[0]) && optimize_insn_for_size_p ()" [(const_int 0)] { int len = GET_MODE_BITSIZE (mode) - INTVAL (operands[3]); -- 2.45.2