* [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
@ 2024-06-18 8:25 pan2.li
2024-06-18 8:25 ` [PATCH v1 2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 pan2.li
0 siblings, 1 reply; 4+ messages in thread
From: pan2.li @ 2024-06-18 8:25 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_11 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-41.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-42.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-43.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-44.c | 25 +++++++++++++++++++
9 files changed, 183 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0f94c5ff087..ab7289a6947 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -2,6 +2,7 @@
#define HAVE_SAT_ARITH
#include <stdint-gcc.h>
+#include <stdbool.h>
/******************************************************************************/
/* Saturation Add (unsigned and signed) */
@@ -140,6 +141,15 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
return !overflow ? ret : 0; \
}
+#define DEF_SAT_U_SUB_FMT_11(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_11 (T x, T y) \
+{ \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -150,5 +160,6 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
+#define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
new file mode 100644
index 00000000000..dd13f94e40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
new file mode 100644
index 00000000000..3ed4195b18b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
new file mode 100644
index 00000000000..b1afaf1fa66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
new file mode 100644
index 00000000000..123f6bde3b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
new file mode 100644
index 00000000000..949bd0d6f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
new file mode 100644
index 00000000000..534795cdd8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
new file mode 100644
index 00000000000..4d0a34fff3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
new file mode 100644
index 00000000000..d74d10dc4e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v1 2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12
2024-06-18 8:25 [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 pan2.li
@ 2024-06-18 8:25 ` pan2.li
0 siblings, 0 replies; 4+ messages in thread
From: pan2.li @ 2024-06-18 8:25 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.
Form 12:
#define DEF_SAT_U_SUB_FMT_12(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_12 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-45.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-46.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-47.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-48.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ab7289a6947..0c2e44af718 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -150,6 +150,15 @@ sat_u_sub_##T##_fmt_11 (T x, T y) \
return overflow ? 0 : ret; \
}
+#define DEF_SAT_U_SUB_FMT_12(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_12 (T x, T y) \
+{ \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, &ret); \
+ return !overflow ? ret : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -161,5 +170,6 @@ sat_u_sub_##T##_fmt_11 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
#define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
+#define RUN_SAT_U_SUB_FMT_12(T, x, y) sat_u_sub_##T##_fmt_12(x, y)
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
new file mode 100644
index 00000000000..1aad8961e29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
new file mode 100644
index 00000000000..d184043f6f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c
new file mode 100644
index 00000000000..033d3b0fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c
new file mode 100644
index 00000000000..135de214710
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c
new file mode 100644
index 00000000000..209965cb8bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12
+
+DEF_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c
new file mode 100644
index 00000000000..80cce95188c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12
+
+DEF_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c
new file mode 100644
index 00000000000..3ecd19c472f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12
+
+DEF_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c
new file mode 100644
index 00000000000..2d7bfc47a31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12
+
+DEF_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
2024-06-19 3:54 [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 =?gb18030?B?1tO+09Xc?=
@ 2024-06-19 6:05 ` Li, Pan2
0 siblings, 0 replies; 4+ messages in thread
From: Li, Pan2 @ 2024-06-19 6:05 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: kito.cheng, jeffreyalaw, rdapp.gcc
[-- Attachment #1: Type: text/plain, Size: 12272 bytes --]
Committed the series, thanks Juzhe.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Wednesday, June 19, 2024 11:55 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; rdapp.gcc <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
lgtm
----------Reply to Message----------
On Tue, Jun 18, 2024 16:25 PM Li, Pan2<pan2.li@intel.com<mailto:pan2.li@intel.com>> wrote:
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_11 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-41.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-42.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-43.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-44.c | 25 +++++++++++++++++++
9 files changed, 183 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0f94c5ff087..ab7289a6947 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -2,6 +2,7 @@
#define HAVE_SAT_ARITH
#include <stdint-gcc.h>
+#include <stdbool.h>
/******************************************************************************/
/* Saturation Add (unsigned and signed) */
@@ -140,6 +141,15 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
return !overflow ? ret : 0; \
}
+#define DEF_SAT_U_SUB_FMT_11(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_11 (T x, T y) \
+{ \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -150,5 +160,6 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
+#define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
new file mode 100644
index 00000000000..dd13f94e40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
new file mode 100644
index 00000000000..3ed4195b18b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
new file mode 100644
index 00000000000..b1afaf1fa66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
new file mode 100644
index 00000000000..123f6bde3b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
new file mode 100644
index 00000000000..949bd0d6f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
new file mode 100644
index 00000000000..534795cdd8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
new file mode 100644
index 00000000000..4d0a34fff3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
new file mode 100644
index 00000000000..d74d10dc4e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
@ 2024-06-19 3:54 =?gb18030?B?1tO+09Xc?=
2024-06-19 6:05 ` Li, Pan2
0 siblings, 1 reply; 4+ messages in thread
From: =?gb18030?B?1tO+09Xc?= @ 2024-06-19 3:54 UTC (permalink / raw)
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lgtm
----------Reply to Message----------
On Tue, Jun 18, 2024 16:25 PM Li, Pan2<pan2.li@intel.com> wrote:
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_11 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-41.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-42.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-43.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-44.c | 25 +++++++++++++++++++
9 files changed, 183 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0f94c5ff087..ab7289a6947 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -2,6 +2,7 @@
#define HAVE_SAT_ARITH
#include <stdint-gcc.h>
+#include <stdbool.h>
/******************************************************************************/
/* Saturation Add (unsigned and signed) */
@@ -140,6 +141,15 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
return !overflow ? ret : 0; \
}
+#define DEF_SAT_U_SUB_FMT_11(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_11 (T x, T y) \
+{ \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -150,5 +160,6 @@ sat_u_sub_##T##_fmt_10 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
+#define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
new file mode 100644
index 00000000000..dd13f94e40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-41.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
new file mode 100644
index 00000000000..3ed4195b18b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-42.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
new file mode 100644
index 00000000000..b1afaf1fa66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
new file mode 100644
index 00000000000..123f6bde3b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-44.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_11:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_11(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
new file mode 100644
index 00000000000..949bd0d6f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-41.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
new file mode 100644
index 00000000000..534795cdd8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-42.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
new file mode 100644
index 00000000000..4d0a34fff3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-43.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
new file mode 100644
index 00000000000..d74d10dc4e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-44.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_11
+
+DEF_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
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2024-06-18 8:25 [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 pan2.li
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2024-06-19 6:05 ` Li, Pan2
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