From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by sourceware.org (Postfix) with ESMTPS id A41523882657 for ; Tue, 18 Jun 2024 08:25:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A41523882657 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A41523882657 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718699164; cv=none; b=WNla2+7lOqzuwwcVxI2Zei3zWycFzvxqPNsu8xOl1qK05ytv1vci2KXE0i7/A+VlI+RGY1CXkLrI0FvT7RLx1ucAJDEtZfDuzHxUDTZmXSz3ZtUyq5E5AaZ7iDS4Isenj0sTtDhUUr6bbGRjfXaenNmq4K9FiVNaReQLnQpgi6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718699164; c=relaxed/simple; bh=UTPa2vSfZhbtVRIfZ1ZX0yvwzMW8Ijf3hjJFlxqozhU=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=yBVaRbQWJG+K+QTLS5geU0KRp9Ne3jKMaeKw6cthmt55CSBlINQYXDGNQmaQDG9/kPwBX7ZrWRZB0W6k5OMNd71fcygbyavBvZ3hjresn6BDyC7ovcyicIn9b0/btmfLo7v1qN1S/OzHOxSgBPawWVvZN1+H2CBowWVu3WDy9n4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718699146; x=1750235146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UTPa2vSfZhbtVRIfZ1ZX0yvwzMW8Ijf3hjJFlxqozhU=; b=dXtu2bVq0hDC3WwrlW/C5H28dpuyGvTMM1jNS+iWZ6fu+pF1k43Pn/+Q MLLF3u0BOuEANFd9rDPM1bzDB7dIOyaO6XxCHvv6GMKO+oSHsidwJG9oo MFLIERL4ovZwOLH3KDgcnrELuQJNrC13EwMabxkLVXx7xtIl8eXNc+NTg Jr6eowzS3rjsfDa2fQPToJrkL86Zny2zjEH2Y5hti6qSYbRtpCVvuY8tE Y3dliAJO9dcaZdmL7HPiH1T5PWikVRZqdifOdK7zRt06v/MnSC4p3DHZm gdNySmg4+XkTYXleb/9AoMBrxYNzOS9Y6HZ726EAm6pPBU5yJcIhpusLT w==; X-CSE-ConnectionGUID: jMdLVnJOTMyYu/PIHATYRA== X-CSE-MsgGUID: dmgwg37pRzKxfwf2zNFS3Q== X-IronPort-AV: E=McAfee;i="6700,10204,11106"; a="19379218" X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="19379218" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2024 01:25:45 -0700 X-CSE-ConnectionGUID: SPIDbddxQn6KDLP5MJYTYA== X-CSE-MsgGUID: 910rxf0QQLSkGx1fSp29/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="46011188" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa004.fm.intel.com with ESMTP; 18 Jun 2024 01:25:44 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 1635E10085DD; Tue, 18 Jun 2024 16:25:42 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 Date: Tue, 18 Jun 2024 16:25:38 +0800 Message-Id: <20240618082538.1744444-2-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618082538.1744444-1-pan2.li@intel.com> References: <20240618082538.1744444-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li After the middle-end support the form 12 of unsigned SAT_SUB and the RISC-V backend implement the SAT_SUB for vector mode, add more test case to cover the form 12. Form 12: #define DEF_SAT_U_SUB_FMT_12(T) \ T __attribute__((noinline)) \ sat_u_sub_##T##_fmt_12 (T x, T y) \ { \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for testing. * gcc.target/riscv/sat_u_sub-45.c: New test. * gcc.target/riscv/sat_u_sub-46.c: New test. * gcc.target/riscv/sat_u_sub-47.c: New test. * gcc.target/riscv/sat_u_sub-48.c: New test. * gcc.target/riscv/sat_u_sub-run-45.c: New test. * gcc.target/riscv/sat_u_sub-run-46.c: New test. * gcc.target/riscv/sat_u_sub-run-47.c: New test. * gcc.target/riscv/sat_u_sub-run-48.c: New test. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c | 19 ++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 18 +++++++++++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c | 17 +++++++++++++ .../gcc.target/riscv/sat_u_sub-run-45.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-46.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-47.c | 25 +++++++++++++++++++ .../gcc.target/riscv/sat_u_sub-run-48.c | 25 +++++++++++++++++++ 9 files changed, 182 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index ab7289a6947..0c2e44af718 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -150,6 +150,15 @@ sat_u_sub_##T##_fmt_11 (T x, T y) \ return overflow ? 0 : ret; \ } +#define DEF_SAT_U_SUB_FMT_12(T) \ +T __attribute__((noinline)) \ +sat_u_sub_##T##_fmt_12 (T x, T y) \ +{ \ + T ret; \ + bool overflow = __builtin_sub_overflow (x, y, &ret); \ + return !overflow ? ret : 0; \ +} + #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y) #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y) #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y) @@ -161,5 +170,6 @@ sat_u_sub_##T##_fmt_11 (T x, T y) \ #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y) #define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y) #define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y) +#define RUN_SAT_U_SUB_FMT_12(T, x, y) sat_u_sub_##T##_fmt_12(x, y) #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c new file mode 100644 index 00000000000..1aad8961e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint8_t_fmt_12: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*a0,\s*[atx][0-9]+ +** andi\s+a0,\s*a0,\s*0xff +** ret +*/ +DEF_SAT_U_SUB_FMT_12(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c new file mode 100644 index 00000000000..d184043f6f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint16_t_fmt_12: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slli\s+a0,\s*a0,\s*48 +** srli\s+a0,\s*a0,\s*48 +** ret +*/ +DEF_SAT_U_SUB_FMT_12(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c new file mode 100644 index 00000000000..033d3b0fb76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint32_t_fmt_12: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_U_SUB_FMT_12(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c new file mode 100644 index 00000000000..135de214710 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_u_sub_uint64_t_fmt_12: +** sub\s+[atx][0-9]+,\s*a0,\s*a1 +** sltu\s+[atx][0-9]+,\s*a0,\s*a1 +** addi\s+a0,\s*[atx][0-9]+,\s*-1 +** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_U_SUB_FMT_12(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c new file mode 100644 index 00000000000..209965cb8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint8_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12 + +DEF_SAT_U_SUB_FMT_12(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 255, 254, 1, }, + { 255, 255, 0, }, + { 254, 255, 0, }, + { 253, 254, 0, }, + { 0, 255, 0, }, + { 1, 255, 0, }, + { 32, 5, 27, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c new file mode 100644 index 00000000000..80cce95188c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint16_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12 + +DEF_SAT_U_SUB_FMT_12(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 65535, 65534, 1, }, + { 65535, 65535, 0, }, + { 65534, 65535, 0, }, + { 65533, 65534, 0, }, + { 0, 65535, 0, }, + { 1, 65535, 0, }, + { 35, 5, 30, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c new file mode 100644 index 00000000000..3ecd19c472f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint32_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12 + +DEF_SAT_U_SUB_FMT_12(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 4294967295, 4294967294, 1, }, + { 4294967295, 4294967295, 0, }, + { 4294967294, 4294967295, 0, }, + { 4294967293, 4294967294, 0, }, + { 1, 4294967295, 0, }, + { 2, 4294967295, 0, }, + { 5, 1, 4, }, +}; + +#include "scalar_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c new file mode 100644 index 00000000000..2d7bfc47a31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +#define T uint64_t +#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_12 + +DEF_SAT_U_SUB_FMT_12(T) + +T test_data[][3] = { + /* arg_0, arg_1, expect */ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 0, }, + { 18446744073709551615u, 18446744073709551614u, 1, }, + { 18446744073709551615u, 18446744073709551615u, 0, }, + { 18446744073709551614u, 18446744073709551615u, 0, }, + { 18446744073709551613u, 18446744073709551614u, 0, }, + { 0, 18446744073709551615u, 0, }, + { 1, 18446744073709551615u, 0, }, + { 43, 11, 32, }, +}; + +#include "scalar_sat_binary.h" -- 2.34.1