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Wed, 19 Jun 2024 12:30:49 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Subject: [PATCH v2] RISC-V: Remove float vector eqne pattern Date: Wed, 19 Jun 2024 20:30:41 +0800 Message-ID: <20240619123042.1972514-1-demin.han@starfivetech.com> X-Mailer: git-send-email 2.45.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BJSPR01CA0019.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::31) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1110:EE_ X-MS-Office365-Filtering-Correlation-Id: da172c68-a254-489a-8db5-08dc905ba693 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|52116011|366013|41320700010|38350700011; X-Microsoft-Antispam-Message-Info: F91lpM6iWFC7OnjhekXhALLl2+B+1zO0vCHWcZWSzlRRlkferz0w+88QRwmq3DYAlrU91i9iM/ciIh6tW1HwZqBBG2/dXIxAwcI8fnLQx8OVLHZL7s2R/u86nNvyZwYnXpB47qFd96+O3DJcRnsO5HlyFTGxe8MUbLUXtzI6AhR+tXwMeOjXuLJ61TTFfuksQrtzMpGbii0vNRG7t5Evespe1R5FGaqLfPXvw9M5cXo3qiby8csOqqElRXetk/1EDvo//M1e81P7fEYUVmRDSdTVAXteV2EcXkWqX2c/tfa49X2bfLao7TTXMmu4nbWGKZNgq5r9PDIw48b9qtJgZyMK5itI0BrA+p6CvzZN5xHJvpS1nWzIJFCpBuBDaeJLnhzFIqgEGQ4hV0T94E+Sq2Q0dP3h2kHdCvOthZi7KkomqjyaKphVerZHi3b+Y4NL1D0SSRtFVCeM/oIxyoBKolAekRbxJCwRjolXKwK9WPrRO5KCJFbxHcmrW0r0lebQC6P0+eLbpnFQe5QU6tmjITyUD2yj32eHv3/W8qQ9fk/yV56ugAXTfhRznHwawmhomamTuY008b0XGkXYc5BXcoqImBWWalpq/6tml88AG21oD4phh5E4jZ8yewSbdhLz X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230037)(1800799021)(52116011)(366013)(41320700010)(38350700011);DIR:OUT;SFP:1102; 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Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test. Signed-off-by: demin.han --- v2 changes: 1. add test Only intrinsics utilize those removed vf patterns. Auto vectorization use vv format now. The NaN will optimized out before expand in autovec as I tested. .../riscv/riscv-vector-builtins-bases.cc | 4 - gcc/config/riscv/vector.md | 86 ------------------- .../riscv/rvv/base/float-point-cmp-eqne.c | 54 ++++++++++++ 3 files changed, 54 insertions(+), 90 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index b6f6e4ff37e..d414721ede8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1420,10 +1420,6 @@ public: switch (e.op_info->op) { case OP_TYPE_vf: { - if (CODE == EQ || CODE == NE) - return e.use_compare_insn (CODE, code_for_pred_eqne_scalar ( - e.vector_mode ())); - else return e.use_compare_insn (CODE, code_for_pred_cmp_scalar ( e.vector_mode ())); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fbcdf96f038..f8fae6557d9 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7545,92 +7545,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand")) - (match_operand:V_VLSF 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 4 "register_operand" " f")) - (match_operand:V_VLSF 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vmf%B2.vf\t%0,%3,%4,v0.t" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSF - (match_operand: 5 "register_operand" " f, f, f, f, f")) - (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vmf%B3.vf\t%0,%4,%5%p1" - [(set_attr "type" "vfcmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point merge ;; ------------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c new file mode 100644 index 00000000000..572bcb8f291 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +#define CMP_FLOAT_VF_1(ID, S, OP, IMM) \ + vbool##S##_t test_float_1_##ID##_##S (vfloat##S##m1_t op1, size_t vl) \ + { \ + return __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl); \ + } + +CMP_FLOAT_VF_1 (0, 32, eq, 0.0) +CMP_FLOAT_VF_1 (1, 32, eq, 1.0) +CMP_FLOAT_VF_1 (2, 32, eq, __builtin_nanf ("123")) +CMP_FLOAT_VF_1 (3, 32, ne, 0.0) +CMP_FLOAT_VF_1 (4, 32, ne, 1.0) +CMP_FLOAT_VF_1 (5, 32, ne, __builtin_nanf ("123")) + +CMP_FLOAT_VF_1 (0, 64, eq, 0.0) +CMP_FLOAT_VF_1 (1, 64, eq, 1.0) +CMP_FLOAT_VF_1 (2, 64, eq, __builtin_nan ("123")) +CMP_FLOAT_VF_1 (3, 64, ne, 0.0) +CMP_FLOAT_VF_1 (4, 64, ne, 1.0) +CMP_FLOAT_VF_1 (5, 64, ne, __builtin_nan ("123")) + +#define CMP_FLOAT_VF_2(ID, S, OP, IMM) \ + vfloat##S##m1_t test_float_2_##ID##_##S (vfloat##S##m1_t op1, \ + vfloat##S##m1_t op2, size_t vl) \ + { \ + vfloat##S##m1_t op3 = __riscv_vfmv_s_f_f##S##m1 (IMM, vl); \ + vbool##S##_t mask1 = __riscv_vmf##OP##_vf_f##S##m1_b##S (op1, IMM, vl); \ + vbool##S##_t mask2 = __riscv_vmf##OP##_vv_f##S##m1_b##S (op1, op3, vl); \ + vbool##S##_t mask3 = __riscv_vmor (mask1, mask2, vl); \ + return __riscv_vmerge_vvm_f##S##m1_tu (op1, op1, op2, mask3, vl); \ + } + +CMP_FLOAT_VF_2 (0, 32, eq, 0.0) +CMP_FLOAT_VF_2 (1, 32, eq, 1.0) +CMP_FLOAT_VF_2 (2, 32, eq, __builtin_nanf ("123")) +CMP_FLOAT_VF_2 (3, 32, ne, 0.0) +CMP_FLOAT_VF_2 (4, 32, ne, 1.0) +CMP_FLOAT_VF_2 (5, 32, ne, __builtin_nanf ("123")) + +CMP_FLOAT_VF_2 (0, 64, eq, 0.0) +CMP_FLOAT_VF_2 (1, 64, eq, 1.0) +CMP_FLOAT_VF_2 (2, 64, eq, __builtin_nan ("123")) +CMP_FLOAT_VF_2 (3, 64, ne, 0.0) +CMP_FLOAT_VF_2 (4, 64, ne, 1.0) +CMP_FLOAT_VF_2 (5, 64, ne, __builtin_nan ("123")) + +/* { dg-final { scan-assembler-times {vmfeq\.vf} 12 } } */ +/* { dg-final { scan-assembler-times {vmfne\.vf} 12 } } */ +/* { dg-final { scan-assembler-times {vmfeq\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {vmfne\.vv} 6 } } */ -- 2.45.1