From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 5DA05388463E for ; Wed, 19 Jun 2024 13:17:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5DA05388463E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5DA05388463E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718803043; cv=none; b=aKkKxwohHAk/8kYynbkAH3ThUgGGGnaYaXakqQEV/hJ+hA5CdxNORlIeyLiduduuzbh7Qmbpll0GuJEVUcz5fJf5CvOAStynDdZxaN968JaHSTc/eUd96fwYeqeo0VJQYXztrYle2uH0t+sAGUduKDRknmOUb4kRkBOHrb+RLSk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1718803043; c=relaxed/simple; bh=i/K3K28PXVoEC52XUbdRlhy7yURBq75D04s7gZCEHOM=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=RVGFaCQJZQqUt8F7k97kcMurqsBTZpA2EUeEhhW09FcR7Z8N/IcArgT5p4aPhjhitvyCJBW41x1ym1AenXhwIjuLwcf/1Q5f1npe0GNVyqBu5kh9gIcRoQ/cB6+t6aV11wyt9OwXa8pIpfEQx+jagRgSfNbogFdKS0crIvAEcUU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718803040; x=1750339040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=i/K3K28PXVoEC52XUbdRlhy7yURBq75D04s7gZCEHOM=; b=gdh3ijWZ/Sd/7NEWtVwMYVwNx8Lb90IBfA6iE9v3LivegqjxwN08SSFA kBFB6ig5hP29pNV9CAgcKJVSritGPXR09H5RJDIluym5I986yiVtCfSqh 99O+DUJG2/HN23kA1WwFe6J5LpHnPjyvdkxpqHNX13G2vABFR3GvSVJWe ulVVawpKq7YUkNd74Sy1jyNEy/1PXxIwSP0pj0DkyPFlk/F60SA2yQxQW L29fMC1Eg3135+6uXjV1p9jkjiucjVGYtrWVlHggl0Lk6GBZ9sZYzsT2j JOEs/9d1Aoy6KdRTGShwoxA9x4/NYJpY38ooKCFC8FPnjf9DjL1LXdCzn g==; X-CSE-ConnectionGUID: EOD2sCYRTTSF+POqMAcKPQ== X-CSE-MsgGUID: 3ysaB2DMT/6JN1hi2UPi7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453158" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453158" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:18 -0700 X-CSE-ConnectionGUID: r1TbcARGSUuUsxjDx791Yg== X-CSE-MsgGUID: GD/Gef0QSY+YIxD714oQeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368370" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:15 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id EE2B41007373; Wed, 19 Jun 2024 21:17:13 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 3/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 Date: Wed, 19 Jun 2024 21:17:00 +0800 Message-Id: <20240619131705.3874097-3-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_NUMSUBJECT,KAM_SHORT,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 5: #define DEF_VEC_SAT_U_SUB_FMT_5(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x < y ? 0 : x - y; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub-17.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-18.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-19.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-20.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-17.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-18.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-19.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-20.c | 75 +++++++++++++++++++ 9 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index a83f964df0c..b25215c10cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -193,6 +193,19 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_5(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + out[i] = x < y ? 0 : x - y; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -205,4 +218,7 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c new file mode 100644 index 00000000000..8d50f5ff26c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c new file mode 100644 index 00000000000..a431ded301c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c new file mode 100644 index 00000000000..acc7ef2d4f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c new file mode 100644 index 00000000000..d74c0972635 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c new file mode 100644 index 00000000000..12207ad7f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c new file mode 100644 index 00000000000..9614f42417a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c new file mode 100644 index 00000000000..cbaf2b14279 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c new file mode 100644 index 00000000000..e1c59a977f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" -- 2.34.1