From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on20712.outbound.protection.partner.outlook.cn [IPv6:2406:e500:4420:2::712]) by sourceware.org (Postfix) with ESMTPS id B2DDF3858C41 for ; Thu, 20 Jun 2024 03:28:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B2DDF3858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B2DDF3858C41 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=2406:e500:4420:2::712 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1718854106; cv=pass; b=C4pFzisgnANJ2ZN53jEjh3P6utNWaDnAC9fJyvzK+kvvkKNMO0PkYXj5YzKuHKfOxOIrih9ur2xneRD34kNfSkkOlo6elT2Y65NAzz9PT0A0QXN6jexqBuTaM08N4pEi8xUjyJWtM+NdoD8UZxZ2/4SxaFkAwbhXxp+QnEc3eg8= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1718854106; c=relaxed/simple; bh=RfoRmwJCEJQqHXPqlJ8RFr01ZllFXK0NXb6UPARDuDI=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=SGv4MeeAeYw4i6Vftqe9/7KtYOMHIGeOXqA5fdplyWucGgTfS0XNEl0AT93xh28dFlVw0LnERTaYEeSInJTMrMkzJWI3qF90A2CFiAnTjJ1omoiqPnEdgjlIzjevrhBXH1kerSAC0e6V2sd9sDItSB00l7lEse79NBf5vpctZxU= ARC-Authentication-Results: i=2; server2.sourceware.org ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hxmwEZkork23OVUsuy5h5L098dfds0J047Q1AYNGvGAxDHe0Jnnk0Q9YgoK6zROYMuW6Sydx5VGYA6SmZzwdnhnTnGYm2X8CbfLItx8r30aYB6HRiE5ojkFxlWtmBndonwgBdr2jEFjcEGxzwmOzq5rELZ+Ib26SA+qXE6t9SarqFgbc8T5ujthsj286aXahN6YwMOjJroeY8mqA457yBN9R36AEOEDutte98CsvQpObyEV70rOzunOOdybri4TLR0DWqiueelJFS2qSV3S+MU46AA3Ue/qcbdktI2kNNdpLxyC+qcd4b9QHUhVAbY2ISYkEoVijNJ+91uqvHl9cOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uC8pl9/lV/IzGVRLNPAA1GHte2IVXtP7uvdHEivd0Qw=; b=LCKU/8zgAXf4J0HN/v7WfwE4FJSoyJIJ3dabrHkSOiX2jWn3HkhkXdx1MfZv1fmxZ3Igp9ATILTdZ5oIlq2GK3Vgg/iopTBft0MxrBYRGCUTYJ+0oSKHEoMUfaccJL3ebDhg5sR3JGflsg2cESB46VUWqEP4OFMZKMk8xultnCn6Nj9Ai++0hnmXawNMufmDkHrBICXo6gzJmKHdG3JsaLnf0VewnWY1njUfcmRN5G7IlMKogi9/a+17H5c8s95kAjrO30QILn1yO+3Je8FM9GaJtj+wHV46subUXoGzNPdoksbu4kNpZSJ8Rfi222o5xrUl24d7/szrpmmC0cHqDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) by ZQ0PR01MB1285.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1a::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7656.33; Thu, 20 Jun 2024 03:28:12 +0000 Received: from ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::99de:1b2a:5786:8dc3]) by ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn ([fe80::99de:1b2a:5786:8dc3%7]) with mapi id 15.20.7656.033; Thu, 20 Jun 2024 03:28:12 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Subject: [PATCH v2] RISC-V: Remove integer vector eqne pattern Date: Thu, 20 Jun 2024 11:28:20 +0800 Message-ID: <20240620032820.203996-1-demin.han@starfivetech.com> X-Mailer: git-send-email 2.45.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0030.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::15) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1285:EE_ X-MS-Office365-Filtering-Correlation-Id: d48fe12b-e906-4de5-a481-08dc90d903a6 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230037|366013|41320700010|52116011|1800799021|38350700011; X-Microsoft-Antispam-Message-Info: hNQkcDwDNiCSF2XgGdVHREBP/nVhEtKkMiNF1MeLJyo0B8ZxPq5Wtj9PD1kmCbOOwnwbXPdJAUlNrsJj6wWeHVBv3yL3FovGhW756z4PyN/M8m1GtCtlzIlBhHwdTfc+FZ4yg7hpQbmFy5+aXzHXtDnwklx+YNDChw2Vg0IGhS8jrohU4ncKKKeHvxP/rhImxYTpPxEDCLjv+MfKjqX67OBxCe0Veb2FH7AudLUH0bAM9M9Z0jcpXSknBVJhGvCOykKWYVGoUJ8Vlt86qcyp2OoCqjm3hVAkIYGJUKjKcRQXELY9tREakjjEvxO1DVZkLQUP4TJ0gwg8d9J0ZRFFy8zavn/D11Is91zUqjUElPHcCDoNZD+1cmp3olGRStswaRE4LjZm4jLmCGH6MHMKoSnKlhwsO1QeBcJg/DZuH99lGLI3t+5QZsoygnsT2AF9IN6pJYk0+sU/00ebnwh61Ad3c3GETF8O9GQJ4V9hSjSoMUxVjuzjPvTWH4MRUzFCtPPoiwHvL2e4r8SxsWo8S08Kl846R5JmqXIc/cFVe5ZteAX93aYzByre1N3x9S2tTAgVlu1Y8QMjVt8+JGZogDSP69ioaa1MAuKQvCqL1cTiQYovmhwUWQj2Jk2exNTo X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230037)(366013)(41320700010)(52116011)(1800799021)(38350700011);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?FXuX6312f/s0NOjwzjKqeYcQliTSNyhcOqqFNxpPbooWPO14Q7YPnQHCrXVP?= =?us-ascii?Q?Y9tpFRpItCb2Wh7We/lxhqlk1mqn27bECk3mbIb3D2zJrTZkXUmgH7v5h7x9?= =?us-ascii?Q?mvxFndto4gk6xbR9nudRmyDi+r4VG0V71vQcQodiTCDUo+iMzgwFVNOC4dUO?= =?us-ascii?Q?g0EEGm8mGggMrOIu9FxlQGEfyvpFwnHgf7GFsxxwvcE+qwl+/CEzNBMDM/2s?= =?us-ascii?Q?nlGvO8W/i3llDYJMgBKImi7C5WMQyl4Xrr3ECDKEgvNzT40e/DM906MNGJAi?= =?us-ascii?Q?9csGXWfb7lNQIl/d80Fl263VB0FX+aKWY21TQXudpXNi15uehvwrA5yBtP8i?= =?us-ascii?Q?nZdNE89d0zoi/urFgrr6fNMN/bEjojJFwUAhV44IlMSScKVc+13O0QQz7RXL?= =?us-ascii?Q?kHJTPGNkMxa69I+AXEVuuELz+snEyEbWMsuhd3PHy+96H2aUQ8UhoD8J1wtG?= =?us-ascii?Q?BrzA549DEPqy7zV2mBh6VxWcFQoSka7jaY27fMFs/aIVy8mD8di/7mYZqGBJ?= =?us-ascii?Q?GzqZWvLzQ8EWhgJ/RR3zKWVPuduwzJBcoSFiicc0z1ycTYOyOLWCaeTeH6/X?= =?us-ascii?Q?MCGbuMKz2rfadLMz2Pjh/LK+BTQX2CErjV3HeY5eYq2+GN5Qc0tnk0aWdtsF?= =?us-ascii?Q?5/RzAoaBrngPfA5yfEY9UXJeHUdioYixyA1TnSznrN67JhDJSC1I9v28GhrZ?= =?us-ascii?Q?gtPfBxqK/R9pkp7jaXjQYnQb2ZMkvThkBPfQt7VXaSmMXOZ7bSUjo8+72ADn?= =?us-ascii?Q?dFfz2RM8EiGMVjneQdlUP0rn9JCkeQYicXkHWaXOCSgJ/4glgRy2Z6vjIIpu?= =?us-ascii?Q?jKbihGpWUbWEehf+qNKHi8WEz1GLHmdcMOg1EscQtxTX3kQ0RP24OHu1UZSl?= =?us-ascii?Q?mMAnAnY0AiYdm/t6u29rt/48JPzjcsCZJF8Trzyo+frFrt8d/prFBlGIe2Ad?= =?us-ascii?Q?rfn0j9B1KDYxWnVXiM8ZwirSiRAKXh8yq/CKxCdokiE3C490ei7Dlab4jY0v?= =?us-ascii?Q?mIq0YohT3RGyfQ8gMkw+KL1lLjbDyo3tpkQJz0J7bV44+ygxdsfaAtwaNVmU?= =?us-ascii?Q?5AKCd+wjhEcb83Q9BnLEMCUg3/kDLIeNw6eSkmMFBXWCMjRvbiQYGSURmT+0?= =?us-ascii?Q?lpgG/KBclc+PSOo21gxJWuwujaBk7H74ydcDsBqUAmgwAn+xg8WvStO15+xD?= =?us-ascii?Q?6bsycH9mAwVeZ/ktfM+JfK05DPufgiWw/jEliu1eeut2RY3gGqUeRzgaZ9tZ?= =?us-ascii?Q?zmlMHYoaDm/u3LvQR/aO6P8r6xaZ+keIBwpqODLfwA7lSSAnNhJh5hXb0jmG?= =?us-ascii?Q?qmres4ruzWf8HB/xUDHZ/xB27XTTzYtasHTBV13+UGxLTo//SuJDGBkhFW9k?= =?us-ascii?Q?KpVJ3Fz2kXMHz5VKrM+TnEz281OsL1492QufqfVgJEeakj2AOyVUnuThygOg?= =?us-ascii?Q?s0bYJBb8G0YYfPeU6WdbL4mp078Tj8up8Kxsn5pJAFE42HyZrjVG3GUDH4zm?= =?us-ascii?Q?Bb83g5AW0Ps9Hw1teQ0eJGyZbxBbEgFJlzM8BkLZw0CxRZBBsj5c78l6caDM?= =?us-ascii?Q?0ms4LUMYnKKiGERo0184nSelfcORXDm0ZCUsUiYW/RuEUMKE8M9Wshk1guwm?= =?us-ascii?Q?cQ=3D=3D?= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: d48fe12b-e906-4de5-a481-08dc90d903a6 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2024 03:28:12.5321 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WpLXaeTUhNwzLw6w+95ENcOL+pdx7li7S2ZJBbMyXy2eyH/ozJ8Et1NxLXkH+noERaUJJTL2cqUdGMoN/BKom2k3ET744OYe/2qo7/eDgpc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1285 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: We can unify eqne and other comparison operations. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/predicates.md (comparison_except_eqge_operator): Only exclude ge (comparison_except_ge_operator): Ditto * config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern (expand_strcmp): Ditto * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne_scalar): Remove eqne patterns (*pred_eqne_scalar_merge_tie_mask): Ditto (*pred_eqne_scalar): Ditto (*pred_eqne_scalar_narrow): Ditto (*pred_eqne_extended_scalar_merge_tie_mask): Ditto (*pred_eqne_extended_scalar): Ditto (*pred_eqne_extended_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer-cmp-eqne.c: New test. Signed-off-by: demin.han --- v2 changes: 1. add test gcc/config/riscv/predicates.md | 4 +- gcc/config/riscv/riscv-string.cc | 4 +- .../riscv/riscv-vector-builtins-bases.cc | 3 - gcc/config/riscv/vector.md | 279 +----------------- .../riscv/rvv/base/integer-cmp-eqne.c | 66 +++++ 5 files changed, 81 insertions(+), 275 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 0fb5729fdcf..9971fabc587 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -568,8 +568,8 @@ (define_predicate "ltge_operator" (define_predicate "comparison_except_ltge_operator" (match_code "eq,ne,le,leu,gt,gtu")) -(define_predicate "comparison_except_eqge_operator" - (match_code "le,leu,gt,gtu,lt,ltu")) +(define_predicate "comparison_except_ge_operator" + (match_code "eq,ne,le,leu,gt,gtu,lt,ltu")) (define_predicate "ge_operator" (match_code "ge,geu")) diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 83e7afbd693..4702001bd9b 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -1342,7 +1342,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle, /* Compare needle with haystack and store in a mask. */ rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec); rtx vmsops[] = {mask, eq, vec, needle}; - emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode), + emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode), riscv_vector::COMPARE_OP, vmsops, cnt); /* Find the first bit in the mask. */ @@ -1468,7 +1468,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes, = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)), vec1); rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)}; - emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode), + emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode), riscv_vector::COMPARE_OP, vmsops1, cnt); /* Look for vec1 != vec2 (includes vec2[i] == 0). */ diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 596b88cc8a3..6483faba39c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -718,9 +718,6 @@ public: if (CODE == GE || CODE == GEU) return e.use_compare_insn (CODE, code_for_pred_ge_scalar ( e.vector_mode ())); - else if (CODE == EQ || CODE == NE) - return e.use_compare_insn (CODE, code_for_pred_eqne_scalar ( - e.vector_mode ())); else return e.use_compare_insn (CODE, code_for_pred_cmp_scalar ( e.vector_mode ())); diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f8fae6557d9..fe18ee5b5f7 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4704,7 +4704,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand"))]) @@ -4722,7 +4722,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 3 "register_operand" " vr") (vec_duplicate:V_VLSI_QHS (match_operand: 4 "register_operand" " r"))]) @@ -4747,7 +4747,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -4769,7 +4769,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_QHS (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -4780,92 +4780,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand")) - (match_operand:V_VLSI_QHS 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" - {}) - -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_QHS 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_QHS - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since ;; we need to deal with SEW = 64 in RV32 system. (define_expand "@pred_cmp_scalar" @@ -4878,7 +4792,7 @@ (define_expand "@pred_cmp_scalar" (match_operand 8 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand") (vec_duplicate:V_VLSI_D (match_operand: 5 "reg_or_int_operand"))]) @@ -4908,39 +4822,6 @@ (define_expand "@pred_cmp_scalar" DONE; }) -(define_expand "@pred_eqne_scalar" - [(set (match_operand: 0 "register_operand") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 6 "vector_length_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "reg_or_int_operand")) - (match_operand:V_VLSI_D 4 "register_operand")]) - (match_operand: 2 "vector_merge_operand")))] - "TARGET_VECTOR" -{ - enum rtx_code code = GET_CODE (operands[3]); - if (riscv_vector::sew64_scalar_helper ( - operands, - /* scalar op */&operands[5], - /* vl */operands[6], - mode, - riscv_vector::has_vi_variant_p (code, operands[5]), - [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], boardcast_scalar, - operands[6], operands[7], operands[8])); - }, - (riscv_vector::avl_type) INTVAL (operands[8]))) - DONE; -}) - (define_insn "*pred_cmp_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -4951,7 +4832,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (match_operand: 4 "register_operand" " r"))]) @@ -4965,30 +4846,6 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7))]) -(define_insn "*pred_eqne_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 4 "register_operand" " r")) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") @@ -5000,7 +4857,7 @@ (define_insn "*pred_cmp_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r"))]) @@ -5022,7 +4879,7 @@ (define_insn "*pred_cmp_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (match_operand: 5 "register_operand" " r, r, r, r, r"))]) @@ -5033,50 +4890,6 @@ (define_insn "*pred_cmp_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -;; We use early-clobber for source LMUL > dest LMUL. -(define_insn "*pred_eqne_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (match_operand: 5 "register_operand" " r, r, r, r, r")) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode)" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" [(set (match_operand: 0 "register_operand" "=vm") (if_then_else: @@ -5087,7 +4900,7 @@ (define_insn "*pred_cmp_extended_scalar_merge_tie_mask" (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "comparison_except_eqge_operator" + (match_operator: 2 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 3 "register_operand" " vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5113,7 +4926,7 @@ (define_insn "*pred_cmp_extended_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5135,7 +4948,7 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (match_operand 8 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "comparison_except_eqge_operator" + (match_operator: 3 "comparison_except_ge_operator" [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr") (vec_duplicate:V_VLSI_D (sign_extend: @@ -5147,76 +4960,6 @@ (define_insn "*pred_cmp_extended_scalar_narrow" (set_attr "mode" "") (set_attr "spec_restriction" "none,thv,thv,none,none")]) -(define_insn "*pred_eqne_extended_scalar_merge_tie_mask" - [(set (match_operand: 0 "register_operand" "=vm") - (if_then_else: - (unspec: - [(match_operand: 1 "register_operand" " 0") - (match_operand 5 "vector_length_operand" " rK") - (match_operand 6 "const_int_operand" " i") - (match_operand 7 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 2 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 4 "register_operand" " r"))) - (match_operand:V_VLSI_D 3 "register_operand" " vr")]) - (match_dup 1)))] - "TARGET_VECTOR && !TARGET_64BIT" - "vms%B2.vx\t%0,%3,%4,v0.t" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "merge_op_idx" "1") - (set_attr "vl_op_idx" "5") - (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7))]) - -;; We don't use early-clobber for LMUL <= 1 to get better codegen. -(define_insn "*pred_eqne_extended_scalar" - [(set (match_operand: 0 "register_operand" "=vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "thv,thv,rvv,rvv")]) - -(define_insn "*pred_eqne_extended_scalar_narrow" - [(set (match_operand: 0 "register_operand" "=vm, vr, vr, &vr, &vr") - (if_then_else: - (unspec: - [(match_operand: 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 7 "const_int_operand" " i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operator: 3 "equality_operator" - [(vec_duplicate:V_VLSI_D - (sign_extend: - (match_operand: 5 "register_operand" " r, r, r, r, r"))) - (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")]) - (match_operand: 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))] - "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (mode) && !TARGET_64BIT" - "vms%B3.vx\t%0,%4,%5%p1" - [(set_attr "type" "vicmp") - (set_attr "mode" "") - (set_attr "spec_restriction" "none,thv,thv,none,none")]) - ;; GE, vmsge.vx/vmsgeu.vx ;; ;; unmasked va >= x diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c new file mode 100644 index 00000000000..52b844cc29d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer-cmp-eqne.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +#define CMP_VF_1(ID, S, OP) \ + vbool##S##_t test_1_##ID##_##S##_##OP (vint##S##m1_t op1, int##S##_t op2, \ + size_t vl) \ + { \ + return __riscv_vms##OP##_vx_i##S##m1_b##S (op1, op2, vl); \ + } + +CMP_VF_1 (0, 8, eq) +CMP_VF_1 (1, 16, eq) +CMP_VF_1 (2, 32, eq) +CMP_VF_1 (3, 64, eq) + +CMP_VF_1 (0, 8, ne) +CMP_VF_1 (1, 16, ne) +CMP_VF_1 (2, 32, ne) +CMP_VF_1 (3, 64, ne) + +#define CMP_VF_2(ID, S, OP, IMM) \ + vbool##S##_t test_2_##ID##_##S##_##OP (vint##S##m1_t op1, size_t vl) \ + { \ + return __riscv_vms##OP##_vx_i##S##m1_b##S (op1, IMM, vl); \ + } + +CMP_VF_2 (0, 8, eq, -16) +CMP_VF_2 (1, 8, eq, 15) +CMP_VF_2 (2, 8, eq, -17) +CMP_VF_2 (3, 8, eq, 16) +CMP_VF_2 (4, 16, eq, -16) +CMP_VF_2 (5, 16, eq, 15) +CMP_VF_2 (6, 16, eq, -17) +CMP_VF_2 (7, 16, eq, 16) +CMP_VF_2 (8, 32, eq, -16) +CMP_VF_2 (9, 32, eq, 15) +CMP_VF_2 (10, 32, eq, -17) +CMP_VF_2 (11, 32, eq, 16) +CMP_VF_2 (12, 64, eq, -16) +CMP_VF_2 (13, 64, eq, 15) +CMP_VF_2 (14, 64, eq, -17) +CMP_VF_2 (15, 64, eq, 16) + +CMP_VF_2 (0, 8, ne, -16) +CMP_VF_2 (1, 8, ne, 15) +CMP_VF_2 (2, 8, ne, -17) +CMP_VF_2 (3, 8, ne, 16) +CMP_VF_2 (4, 16, ne, -16) +CMP_VF_2 (5, 16, ne, 15) +CMP_VF_2 (6, 16, ne, -17) +CMP_VF_2 (7, 16, ne, 16) +CMP_VF_2 (8, 32, ne, -16) +CMP_VF_2 (9, 32, ne, 15) +CMP_VF_2 (10, 32, ne, -17) +CMP_VF_2 (11, 32, ne, 16) +CMP_VF_2 (12, 64, ne, -16) +CMP_VF_2 (13, 64, ne, 15) +CMP_VF_2 (14, 64, ne, -17) +CMP_VF_2 (15, 64, ne, 16) + +/* { dg-final { scan-assembler-times {vmseq\.vx} 12 } } */ +/* { dg-final { scan-assembler-times {vmsne\.vx} 12 } } */ +/* { dg-final { scan-assembler-times {vmseq\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {vmsne\.vi} 8 } } */ -- 2.45.1