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* [RFC] RISC-V: Add support for Profiles RVA/B23.
@ 2024-07-29  3:24 Jiawei
  2024-07-30 20:48 ` Jeff Law
  2024-08-01 13:54 ` Christoph Müllner
  0 siblings, 2 replies; 6+ messages in thread
From: Jiawei @ 2024-07-29  3:24 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, jlaw, christoph.muellner, palmer, jeff, Jiawei

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], 
which depend on the base RISC-V Profiles support[2].

[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html


gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: New Profiles.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-22.c: New test.
	* gcc.target/riscv/attribute-23.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc       | 20 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++
 gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 23ae07fe2f3..e6e8adf5e1b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
   {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
 
@@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
    "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+     'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+     extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+     'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+     extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part.  */
 
   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c
new file mode 100644
index 00000000000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c
new file mode 100644
index 00000000000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
  2024-07-29  3:24 [RFC] RISC-V: Add support for Profiles RVA/B23 Jiawei
@ 2024-07-30 20:48 ` Jeff Law
  2024-07-31  1:47   ` Jiawei
  2024-08-01 13:54 ` Christoph Müllner
  1 sibling, 1 reply; 6+ messages in thread
From: Jeff Law @ 2024-07-30 20:48 UTC (permalink / raw)
  To: Jiawei, gcc-patches; +Cc: kito.cheng, jlaw, christoph.muellner, palmer, jeff



On 7/28/24 9:24 PM, Jiawei wrote:
> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
> which depend on the base RISC-V Profiles support[2].
> 
> [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
> [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
> 
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc: New Profiles.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/attribute-22.c: New test.
> 	* gcc.target/riscv/attribute-23.c: New test.
So this was discussed in the patch review meeting earlier today.  This 
really needs to wait until the profile is ratified.  So I've put the 
patch into the deferred state for now.

jeff




^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
  2024-07-30 20:48 ` Jeff Law
@ 2024-07-31  1:47   ` Jiawei
  0 siblings, 0 replies; 6+ messages in thread
From: Jiawei @ 2024-07-31  1:47 UTC (permalink / raw)
  To: Jeff Law, gcc-patches; +Cc: kito.cheng, jlaw, christoph.muellner, palmer, jeff


在 2024/7/31 4:48, Jeff Law 写道:
>
>
> On 7/28/24 9:24 PM, Jiawei wrote:
>> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
>> which depend on the base RISC-V Profiles support[2].
>>
>> [1] 
>> https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
>> [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
>>
>>
>> gcc/ChangeLog:
>>
>>     * common/config/riscv/riscv-common.cc: New Profiles.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/attribute-22.c: New test.
>>     * gcc.target/riscv/attribute-23.c: New test.
> So this was discussed in the patch review meeting earlier today. This 
> really needs to wait until the profile is ratified.  So I've put the 
> patch into the deferred state for now.
>
> jeff
>
Appreciate it, I will await further updates on the ratification process.


BR,

jiawei


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
  2024-07-29  3:24 [RFC] RISC-V: Add support for Profiles RVA/B23 Jiawei
  2024-07-30 20:48 ` Jeff Law
@ 2024-08-01 13:54 ` Christoph Müllner
  2024-08-02  8:48   ` Jiawei
  2024-08-02 15:39   ` Jiawei
  1 sibling, 2 replies; 6+ messages in thread
From: Christoph Müllner @ 2024-08-01 13:54 UTC (permalink / raw)
  To: Jiawei; +Cc: gcc-patches, kito.cheng, jlaw, palmer, jeff

On Mon, Jul 29, 2024 at 5:26 AM Jiawei <jiawei@iscas.ac.cn> wrote:
>
> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
> which depend on the base RISC-V Profiles support[2].
>
> [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
> [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
>
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc: New Profiles.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/attribute-22.c: New test.
>         * gcc.target/riscv/attribute-23.c: New test.
>
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 20 +++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++
>  gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++
>  3 files changed, 41 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 23ae07fe2f3..e6e8adf5e1b 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
>    {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
> +

Independent of the fact that this will be delayed until ratification:
I would prefer to have this in a separate patch as Zimop and Zcmop are
dependencies.
Since Zimop and Zcmop are already ratified, this does not have a
dependency for the profiles ratification.


>    {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>    {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
>
> @@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
>     "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>     "_zicboz_zfhmin_zkt"},
>
> +  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
> +     'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
> +     extensions.  */
> +  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
> +   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
> +   "_zfa_zawrs"},
> +
> +
> +  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
> +     'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
> +     extensions.  */
> +  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
> +   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
> +   "_zfa_zawrs"},
> +
>    /* Currently we do not define S/M mode Profiles in gcc part.  */
>
>    /* Terminate the list.  */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c
> new file mode 100644
> index 00000000000..0bbb3242ddd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
> +
> +void foo(){}
> +
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
> +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
> +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
> +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
> +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
> +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c
> new file mode 100644
> index 00000000000..459b5641ca3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
> +
> +void foo(){}
> +
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
> +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
> +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
> +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
> +"_zbb1p0_zbs1p0_zkt1p0\"" } } */
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
  2024-08-01 13:54 ` Christoph Müllner
@ 2024-08-02  8:48   ` Jiawei
  2024-08-02 15:39   ` Jiawei
  1 sibling, 0 replies; 6+ messages in thread
From: Jiawei @ 2024-08-02  8:48 UTC (permalink / raw)
  To: Christoph Müllner; +Cc: gcc-patches, kito.cheng, jlaw, palmer, jeff


在 2024/8/1 21:54, Christoph Müllner 写道:
> On Mon, Jul 29, 2024 at 5:26 AM Jiawei <jiawei@iscas.ac.cn> wrote:
>> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
>> which depend on the base RISC-V Profiles support[2].
>>
>> [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
>> [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
>>
>>
>> gcc/ChangeLog:
>>
>>          * common/config/riscv/riscv-common.cc: New Profiles.
>>
>> gcc/testsuite/ChangeLog:
>>
>>          * gcc.target/riscv/attribute-22.c: New test.
>>          * gcc.target/riscv/attribute-23.c: New test.
>>
>> ---
>>   gcc/common/config/riscv/riscv-common.cc       | 20 +++++++++++++++++++
>>   gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++
>>   gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++
>>   3 files changed, 41 insertions(+)
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
>> index 23ae07fe2f3..e6e8adf5e1b 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>>     {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
>>     {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>>
>> +  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
>> +  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
>> +
> Independent of the fact that this will be delayed until ratification:
> I would prefer to have this in a separate patch as Zimop and Zcmop are
> dependencies.
> Since Zimop and Zcmop are already ratified, this does not have a
> dependency for the profiles ratification.

Ok, I will split it into another patch, thanks!

Jiawei

>
>
>>     {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>>     {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
>>
>> @@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
>>      "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>>      "_zicboz_zfhmin_zkt"},
>>
>> +  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
>> +     'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
>> +     extensions.  */
>> +  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>> +   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
>> +   "_zfa_zawrs"},
>> +
>> +
>> +  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
>> +     'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
>> +     extensions.  */
>> +  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>> +   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
>> +   "_zfa_zawrs"},
>> +
>>     /* Currently we do not define S/M mode Profiles in gcc part.  */
>>
>>     /* Terminate the list.  */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c
>> new file mode 100644
>> index 00000000000..0bbb3242ddd
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
>> @@ -0,0 +1,11 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
>> +
>> +void foo(){}
>> +
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
>> +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
>> +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
>> +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
>> +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
>> +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c
>> new file mode 100644
>> index 00000000000..459b5641ca3
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
>> @@ -0,0 +1,10 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
>> +
>> +void foo(){}
>> +
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
>> +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
>> +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
>> +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
>> +"_zbb1p0_zbs1p0_zkt1p0\"" } } */
>> --
>> 2.25.1
>>


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [RFC] RISC-V: Add support for Profiles RVA/B23.
  2024-08-01 13:54 ` Christoph Müllner
  2024-08-02  8:48   ` Jiawei
@ 2024-08-02 15:39   ` Jiawei
  1 sibling, 0 replies; 6+ messages in thread
From: Jiawei @ 2024-08-02 15:39 UTC (permalink / raw)
  To: Christoph Müllner; +Cc: gcc-patches, kito.cheng, jlaw, palmer, jeff


在 2024/8/1 21:54, Christoph Müllner 写道:
> On Mon, Jul 29, 2024 at 5:26 AM Jiawei <jiawei@iscas.ac.cn> wrote:
>> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
>> which depend on the base RISC-V Profiles support[2].
>>
>> [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
>> [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html
>>
>>
>> gcc/ChangeLog:
>>
>>          * common/config/riscv/riscv-common.cc: New Profiles.
>>
>> gcc/testsuite/ChangeLog:
>>
>>          * gcc.target/riscv/attribute-22.c: New test.
>>          * gcc.target/riscv/attribute-23.c: New test.
>>
>> ---
>>   gcc/common/config/riscv/riscv-common.cc       | 20 +++++++++++++++++++
>>   gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++
>>   gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++
>>   3 files changed, 41 insertions(+)
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
>> index 23ae07fe2f3..e6e8adf5e1b 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>>     {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
>>     {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>>
>> +  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
>> +  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
>> +
> Independent of the fact that this will be delayed until ratification:
> I would prefer to have this in a separate patch as Zimop and Zcmop are
> dependencies.
> Since Zimop and Zcmop are already ratified, this does not have a
> dependency for the profiles ratification.

Thanks for your advice, implemented Zimop extension  in new patch

https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659280.html

>
>
>>     {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>>     {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
>>
>> @@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
>>      "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>>      "_zicboz_zfhmin_zkt"},
>>
>> +  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
>> +     'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
>> +     extensions.  */
>> +  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>> +   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
>> +   "_zfa_zawrs"},
>> +
>> +
>> +  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
>> +     'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
>> +     extensions.  */
>> +  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
>> +   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
>> +   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
>> +   "_zfa_zawrs"},
>> +
>>     /* Currently we do not define S/M mode Profiles in gcc part.  */
>>
>>     /* Terminate the list.  */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c
>> new file mode 100644
>> index 00000000000..0bbb3242ddd
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
>> @@ -0,0 +1,11 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
>> +
>> +void foo(){}
>> +
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
>> +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
>> +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
>> +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
>> +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
>> +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
>> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c
>> new file mode 100644
>> index 00000000000..459b5641ca3
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
>> @@ -0,0 +1,10 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
>> +
>> +void foo(){}
>> +
>> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
>> +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
>> +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
>> +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
>> +"_zbb1p0_zbs1p0_zkt1p0\"" } } */
>> --
>> 2.25.1
>>


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2024-08-02 15:39 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-07-29  3:24 [RFC] RISC-V: Add support for Profiles RVA/B23 Jiawei
2024-07-30 20:48 ` Jeff Law
2024-07-31  1:47   ` Jiawei
2024-08-01 13:54 ` Christoph Müllner
2024-08-02  8:48   ` Jiawei
2024-08-02 15:39   ` Jiawei

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