* [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
@ 2024-08-18 6:10 pan2.li
2024-08-18 6:10 ` [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 pan2.li
2024-08-18 15:21 ` [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 Jeff Law
0 siblings, 2 replies; 9+ messages in thread
From: pan2.li @ 2024-08-18 6:10 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 2. Aka:
Form 2:
#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
{ \
WT max = (WT)(NT)-1; \
return x > max ? (NT) max : (NT)x; \
}
QUAD:
DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
OCT:
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_trunc-10.c: New test.
* gcc.target/riscv/sat_u_trunc-11.c: New test.
* gcc.target/riscv/sat_u_trunc-12.c: New test.
* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
* gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/sat_u_trunc-10.c | 17 ++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-11.c | 17 ++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-12.c | 20 +++++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-10.c | 16 +++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-11.c | 16 +++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-12.c | 16 +++++++++++++++
6 files changed, 102 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
new file mode 100644
index 00000000000..7dfc740c54f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
new file mode 100644
index 00000000000..c50ae96f47d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
new file mode 100644
index 00000000000..61331cee6fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
new file mode 100644
index 00000000000..4bc9303e457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
new file mode 100644
index 00000000000..a2afdb9ab22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c
new file mode 100644
index 00000000000..699485cf139
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint16_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3
2024-08-18 6:10 [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 pan2.li
@ 2024-08-18 6:10 ` pan2.li
2024-08-18 15:21 ` [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 Jeff Law
1 sibling, 0 replies; 9+ messages in thread
From: pan2.li @ 2024-08-18 6:10 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 3. Aka:
Form 3:
#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
NT __attribute__((noinline)) \
sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
{ \
WT max = (WT)(NT)-1; \
return x <= max ? (NT)x : (NT) max; \
}
QUAD:
DEF_SAT_U_TRUC_FMT_3 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint32_t)
OCT:
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_trunc-16.c: New test.
* gcc.target/riscv/sat_u_trunc-17.c: New test.
* gcc.target/riscv/sat_u_trunc-18.c: New test.
* gcc.target/riscv/sat_u_trunc-run-16.c: New test.
* gcc.target/riscv/sat_u_trunc-run-17.c: New test.
* gcc.target/riscv/sat_u_trunc-run-18.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../gcc.target/riscv/sat_u_trunc-16.c | 17 ++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-17.c | 17 ++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-18.c | 20 +++++++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-16.c | 16 +++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-17.c | 16 +++++++++++++++
.../gcc.target/riscv/sat_u_trunc-run-18.c | 16 +++++++++++++++
6 files changed, 102 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-18.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
new file mode 100644
index 00000000000..3ee7dc03ade
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
new file mode 100644
index 00000000000..975853712cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
new file mode 100644
index 00000000000..11e34ae6fd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
new file mode 100644
index 00000000000..3edcf137a79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUC_FMT_3_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_3_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-17.c
new file mode 100644
index 00000000000..92bf7ae43e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-17.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUC_FMT_3_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_3_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-18.c
new file mode 100644
index 00000000000..3db5fdfffe8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-18.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint16_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUC_FMT_3_WRAP(T1, T2)
+
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x) RUN_SAT_U_TRUC_FMT_3_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-18 6:10 [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 pan2.li
2024-08-18 6:10 ` [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 pan2.li
@ 2024-08-18 15:21 ` Jeff Law
2024-08-19 1:24 ` Li, Pan2
1 sibling, 1 reply; 9+ messages in thread
From: Jeff Law @ 2024-08-18 15:21 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc
On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add test cases for the unsigned scalar quad and
> oct .SAT_TRUNC form 2. Aka:
>
> Form 2:
> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
> NT __attribute__((noinline)) \
> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
> { \
> WT max = (WT)(NT)-1; \
> return x > max ? (NT) max : (NT)x; \
> }
>
> QUAD:
> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>
> OCT:
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_u_trunc-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-12.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Looks like they're failing in the upstream pre-commit tester:
> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-18 15:21 ` [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 Jeff Law
@ 2024-08-19 1:24 ` Li, Pan2
2024-08-19 2:49 ` Li, Pan2
0 siblings, 1 reply; 9+ messages in thread
From: Li, Pan2 @ 2024-08-19 1:24 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc
Opps, let me double check what happened to my local tester.
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Sunday, August 18, 2024 11:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add test cases for the unsigned scalar quad and
> oct .SAT_TRUNC form 2. Aka:
>
> Form 2:
> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
> NT __attribute__((noinline)) \
> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
> { \
> WT max = (WT)(NT)-1; \
> return x > max ? (NT) max : (NT)x; \
> }
>
> QUAD:
> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>
> OCT:
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_u_trunc-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-12.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Looks like they're failing in the upstream pre-commit tester:
> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-19 1:24 ` Li, Pan2
@ 2024-08-19 2:49 ` Li, Pan2
2024-08-19 16:14 ` Patrick O'Neill
0 siblings, 1 reply; 9+ messages in thread
From: Li, Pan2 @ 2024-08-19 2:49 UTC (permalink / raw)
To: Li, Pan2, Jeff Law, gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc
Turn out that the pre-commit doesn't pick up the newest upstream when testing this patch.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Monday, August 19, 2024 9:25 AM
To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
Subject: RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
Opps, let me double check what happened to my local tester.
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Sunday, August 18, 2024 11:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to add test cases for the unsigned scalar quad and
> oct .SAT_TRUNC form 2. Aka:
>
> Form 2:
> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
> NT __attribute__((noinline)) \
> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
> { \
> WT max = (WT)(NT)-1; \
> return x > max ? (NT) max : (NT)x; \
> }
>
> QUAD:
> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>
> OCT:
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_u_trunc-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-12.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Looks like they're failing in the upstream pre-commit tester:
> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-19 2:49 ` Li, Pan2
@ 2024-08-19 16:14 ` Patrick O'Neill
2024-08-20 0:39 ` Li, Pan2
2024-08-28 1:22 ` Li, Pan2
0 siblings, 2 replies; 9+ messages in thread
From: Patrick O'Neill @ 2024-08-19 16:14 UTC (permalink / raw)
To: Li, Pan2, gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Jeff Law
Hi Pan,
Once the postcommit baseline moves forward (trunk is currently failing
to build linux targets [1] [2]) I'll re-trigger precommit for you.
Thanks,
Patrick
[1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409
[2]: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1564
On 8/18/24 19:49, Li, Pan2 wrote:
> Turn out that the pre-commit doesn't pick up the newest upstream when testing this patch.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Monday, August 19, 2024 9:25 AM
> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
> Opps, let me double check what happened to my local tester.
>
> Pan
>
> -----Original Message-----
> From: Jeff Law <jeffreyalaw@gmail.com>
> Sent: Sunday, August 18, 2024 11:21 PM
> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
>
>
> On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
>> From: Pan Li <pan2.li@intel.com>
>>
>> This patch would like to add test cases for the unsigned scalar quad and
>> oct .SAT_TRUNC form 2. Aka:
>>
>> Form 2:
>> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>> NT __attribute__((noinline)) \
>> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>> { \
>> WT max = (WT)(NT)-1; \
>> return x > max ? (NT) max : (NT)x; \
>> }
>>
>> QUAD:
>> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>>
>> OCT:
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>>
>> The below test is passed for this patch.
>> * The rv64gcv regression test.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/sat_u_trunc-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-12.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
> Looks like they're failing in the upstream pre-commit tester:
>
>> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
>
> jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-19 16:14 ` Patrick O'Neill
@ 2024-08-20 0:39 ` Li, Pan2
2024-08-28 1:22 ` Li, Pan2
1 sibling, 0 replies; 9+ messages in thread
From: Li, Pan2 @ 2024-08-20 0:39 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches
Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Jeff Law
Great! Thanks Patrick.
Pan
-----Original Message-----
From: Patrick O'Neill <patrick@rivosinc.com>
Sent: Tuesday, August 20, 2024 12:14 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
Hi Pan,
Once the postcommit baseline moves forward (trunk is currently failing
to build linux targets [1] [2]) I'll re-trigger precommit for you.
Thanks,
Patrick
[1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409
[2]: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1564
On 8/18/24 19:49, Li, Pan2 wrote:
> Turn out that the pre-commit doesn't pick up the newest upstream when testing this patch.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Monday, August 19, 2024 9:25 AM
> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
> Opps, let me double check what happened to my local tester.
>
> Pan
>
> -----Original Message-----
> From: Jeff Law <jeffreyalaw@gmail.com>
> Sent: Sunday, August 18, 2024 11:21 PM
> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
>
>
> On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
>> From: Pan Li <pan2.li@intel.com>
>>
>> This patch would like to add test cases for the unsigned scalar quad and
>> oct .SAT_TRUNC form 2. Aka:
>>
>> Form 2:
>> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>> NT __attribute__((noinline)) \
>> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>> { \
>> WT max = (WT)(NT)-1; \
>> return x > max ? (NT) max : (NT)x; \
>> }
>>
>> QUAD:
>> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>>
>> OCT:
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>>
>> The below test is passed for this patch.
>> * The rv64gcv regression test.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/sat_u_trunc-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-12.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
> Looks like they're failing in the upstream pre-commit tester:
>
>> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
>
> jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-19 16:14 ` Patrick O'Neill
2024-08-20 0:39 ` Li, Pan2
@ 2024-08-28 1:22 ` Li, Pan2
2024-08-28 4:50 ` Patrick O'Neill
1 sibling, 1 reply; 9+ messages in thread
From: Li, Pan2 @ 2024-08-28 1:22 UTC (permalink / raw)
To: Patrick O'Neill, gcc-patches
Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Jeff Law
Hi Patrick,
Could you please help to re-trigger the pre-commit?
Thanks in advance!
Pan
-----Original Message-----
From: Patrick O'Neill <patrick@rivosinc.com>
Sent: Tuesday, August 20, 2024 12:14 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
Hi Pan,
Once the postcommit baseline moves forward (trunk is currently failing
to build linux targets [1] [2]) I'll re-trigger precommit for you.
Thanks,
Patrick
[1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409
[2]: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1564
On 8/18/24 19:49, Li, Pan2 wrote:
> Turn out that the pre-commit doesn't pick up the newest upstream when testing this patch.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Monday, August 19, 2024 9:25 AM
> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
> Opps, let me double check what happened to my local tester.
>
> Pan
>
> -----Original Message-----
> From: Jeff Law <jeffreyalaw@gmail.com>
> Sent: Sunday, August 18, 2024 11:21 PM
> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
> Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
>
>
> On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
>> From: Pan Li <pan2.li@intel.com>
>>
>> This patch would like to add test cases for the unsigned scalar quad and
>> oct .SAT_TRUNC form 2. Aka:
>>
>> Form 2:
>> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>> NT __attribute__((noinline)) \
>> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>> { \
>> WT max = (WT)(NT)-1; \
>> return x > max ? (NT) max : (NT)x; \
>> }
>>
>> QUAD:
>> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>>
>> OCT:
>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>>
>> The below test is passed for this patch.
>> * The rv64gcv regression test.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/sat_u_trunc-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-12.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
>> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
> Looks like they're failing in the upstream pre-commit tester:
>
>> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
>
> jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
2024-08-28 1:22 ` Li, Pan2
@ 2024-08-28 4:50 ` Patrick O'Neill
0 siblings, 0 replies; 9+ messages in thread
From: Patrick O'Neill @ 2024-08-28 4:50 UTC (permalink / raw)
To: Li, Pan2, gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Jeff Law
Thanks for the ping - It's running now:
https://github.com/ewlu/gcc-precommit-ci/issues/2146
Patrick
On 8/27/24 18:22, Li, Pan2 wrote:
> Hi Patrick,
>
> Could you please help to re-trigger the pre-commit?
> Thanks in advance!
>
> Pan
>
> -----Original Message-----
> From: Patrick O'Neill <patrick@rivosinc.com>
> Sent: Tuesday, August 20, 2024 12:14 AM
> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com; Jeff Law <jeffreyalaw@gmail.com>
> Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>
> Hi Pan,
>
> Once the postcommit baseline moves forward (trunk is currently failing
> to build linux targets [1] [2]) I'll re-trigger precommit for you.
>
> Thanks,
> Patrick
>
> [1]: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116409
> [2]: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1564
>
> On 8/18/24 19:49, Li, Pan2 wrote:
>> Turn out that the pre-commit doesn't pick up the newest upstream when testing this patch.
>>
>> Pan
>>
>> -----Original Message-----
>> From: Li, Pan2 <pan2.li@intel.com>
>> Sent: Monday, August 19, 2024 9:25 AM
>> To: Jeff Law <jeffreyalaw@gmail.com>; gcc-patches@gcc.gnu.org
>> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
>> Subject: RE: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>>
>> Opps, let me double check what happened to my local tester.
>>
>> Pan
>>
>> -----Original Message-----
>> From: Jeff Law <jeffreyalaw@gmail.com>
>> Sent: Sunday, August 18, 2024 11:21 PM
>> To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
>> Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com
>> Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2
>>
>>
>>
>> On 8/18/24 12:10 AM, pan2.li@intel.com wrote:
>>> From: Pan Li <pan2.li@intel.com>
>>>
>>> This patch would like to add test cases for the unsigned scalar quad and
>>> oct .SAT_TRUNC form 2. Aka:
>>>
>>> Form 2:
>>> #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>>> NT __attribute__((noinline)) \
>>> sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>>> { \
>>> WT max = (WT)(NT)-1; \
>>> return x > max ? (NT) max : (NT)x; \
>>> }
>>>
>>> QUAD:
>>> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
>>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
>>>
>>> OCT:
>>> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
>>>
>>> The below test is passed for this patch.
>>> * The rv64gcv regression test.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.target/riscv/sat_u_trunc-10.c: New test.
>>> * gcc.target/riscv/sat_u_trunc-11.c: New test.
>>> * gcc.target/riscv/sat_u_trunc-12.c: New test.
>>> * gcc.target/riscv/sat_u_trunc-run-10.c: New test.
>>> * gcc.target/riscv/sat_u_trunc-run-11.c: New test.
>>> * gcc.target/riscv/sat_u_trunc-run-12.c: New test.
>> Looks like they're failing in the upstream pre-commit tester:
>>
>>> https://github.com/ewlu/gcc-precommit-ci/issues/2066#issuecomment-2295137578
>> jeff
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-08-28 4:50 UTC | newest]
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2024-08-19 1:24 ` Li, Pan2
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