From: Jeff Law <jeffreyalaw@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>, Edwin Lu <ewlu@rivosinc.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
Date: Thu, 7 Sep 2023 07:17:21 -0600 [thread overview]
Message-ID: <20ab1f6c-fbfd-4891-9af3-f432d3d545d3@gmail.com> (raw)
In-Reply-To: <089f99be-332f-482e-80d3-cfca2c27c676@irq.a4lg.com>
On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
>
> Looks okay to me but will need to resolve merge conflicts after commit
> af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
> 'Zicond' support").
Sure. We allow trival updates to resolve merge conflicts without
needing another round of review.
Jeff
next prev parent reply other threads:[~2023-09-07 13:17 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-07 17:26 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
2023-09-06 23:33 ` Kito Cheng
2023-09-07 17:29 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
2023-09-06 23:22 ` Kito Cheng
2023-09-07 0:42 ` Tsukasa OI
2023-09-07 13:17 ` Jeff Law [this message]
2023-09-11 17:48 ` [PATCH 3/5][Committed] " Edwin Lu
2023-09-11 17:48 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-11 17:48 ` [PATCH 4/5][Committed] " Edwin Lu
2023-09-11 17:48 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 5/5] RISC-V: Remove Assert Protecting Types Edwin Lu
2023-09-07 13:19 ` Jeff Law
2023-09-07 17:31 ` Edwin Lu
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