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Thu, 18 Jan 2024 12:17:25 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B1DC858052; Thu, 18 Jan 2024 12:17:25 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 10BEE58050; Thu, 18 Jan 2024 12:17:22 +0000 (GMT) Received: from [9.43.80.20] (unknown [9.43.80.20]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jan 2024 12:17:21 +0000 (GMT) Message-ID: <217883bf-6204-4c1f-af65-097142c5c8ad@linux.ibm.com> Date: Thu, 18 Jan 2024 17:47:20 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1] rs6000: New pass for replacement of adjacent (load) lxv with lxvp Content-Language: en-US To: Michael Matz Cc: "Kewen.Lin" , Richard Biener , Peter Bergner , Vladimir Makarov , Michael Meissner , Segher Boessenkool , David Edelsohn , gcc-patches , Richard Sandiford , alex.coplan@arm.com References: <7b7e1da7-19bd-4192-b5a3-db3fed3a0aaf@linux.ibm.com> <00272349-aa2a-4ea3-9859-913b7b4fe049@linux.ibm.com> <0efa1db8-323e-4cdb-9b95-bf6cee25d03d@linux.ibm.com> From: Ajit Agarwal In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jJl_5v8WSMka2MMoK7oOAAZ8wzfSUR1x X-Proofpoint-ORIG-GUID: qYs3P-Yx2mNoKTn6pjPbu5flycjxVjel X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_06,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 malwarescore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180088 X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello Michael: On 17/01/24 7:58 pm, Michael Matz wrote: > Hello, > > On Wed, 17 Jan 2024, Ajit Agarwal wrote: > >>> first is even, since OOmode is only ok for even vsx register and its >>> size makes it take two consecutive vsx registers. >>> >>> Hi Peter, is my understanding correct? >>> >> >> I tried all the combination in the past RA is not allocating sequential >> register. I dont see any such code in RA that generates sequential >> registers. > > See HARD_REGNO_NREGS. If you form a pseudo of a mode that's larger than a > native-sized hardreg (and the target is correctly set up) then the RA will > allocate the correct number of hardregs (consecutively) for this pseudo. > This is what Kewen was referring to by mentioning the OOmode for the new > hypothetical pseudo. The individual parts of such pseudo will then need > to use subreg to access them. > > So, when you work before RA you simply will transform this (I'm going to > use SImode and DImode for demonstration): > > (set (reg:SI x) (mem:SI (addr))) > (set (reg:SI y) (mem:SI (addr+4))) > ... > ( ...use1... (reg:SI x)) > ( ...use2... (reg:SI y)) > > into this: > > (set (reg:DI z) (mem:DI (addr))) > ... > ( ...use1... (subreg:SI (reg:DI z) 0)) > ( ...use2... (subreg:SI (reg:DI z) 4)) > > For this to work the target needs to accept the (subreg...) in certain > operands of instruction patterns, which I assume was what Kewen also > referred to. The register allocator will then assign hardregs X and X+1 > to the pseudo-reg 'z'. (Assuming that DImode is okay for hardreg X, and > HARD_REGNO_NREGS says that it needs two hardregs to hold DImode). > > It will also replace the subregs by their appropriate concrete hardreg. > > It seems your problems stem from trying to place your new pass somewhere > within the register-allocation pipeline, rather than simply completely > before. > Thanks for the suggestions. It worked and with above changes sequential registers are generated by RA pass. I am working on common infrastructure with AARCH64 for register pairs loads and stores pass. Thanks & Regards Ajit > > Ciao, > Michael.