On 12/6/22 02:11, Feng Wang wrote:
> From: wangfeng <wangfeng@eswincomputing.com>
> 
> There is no Immediate operand of ins "rol" according to the B-ext,
> so the immediate operand should be loaded into register at first.
> But we can convert it to the ins "rori" or "roriw", and then one
> immediate load ins can be reduced.
> So I added some conditions when reverse the rotate shift during RTL
> expansion and RTL optimization.Reverse if the below two conditions
> are met at the same time,
> 1. The current insn_code doesn't exist or it's operand doesn't match,
>     or the shift amount is beyond the half size of the machine mode;
> 2. The reversed insn_code exists and it's operand matches.
> 
> Please refer to the following use cases:
> unsigned long foo2(unsigned long rs1)
> {
>      return (rs1 << 10) | (rs1 >> 54);
> }
> 
> The compiler result is:
> li	a1,10
> rol	a0,a0,a1
> 
> This patch will generate one ins
> rori a0,a0,54
> 
> At the same time I add the missing "roriw" ins RTL pattern
> 
> Pass the linux-rv32imafdc-ilp32d-medany,linux-rv64imafdc-lp64d-medany,
> newlib-rv32imafc-ilp32f-medany and newlib-rv64imafdc-lp64d-medany regression.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/bitmanip.md:  Add "roriw" insn output
>          * expmed.cc (expand_shift_1):Call reverse_rotate_by_imm_p to judge
>                     whether reverse the rotate direction when GIMPLE to RTL.
>          * rtl.h (reverse_rotate_by_imm_p): Add function declartion
>          * simplify-rtx.cc (reverse_rotate_by_imm_p): Add a function to judge
>                 whether reverse rotate shift direction when simplify rtx.
>                 Reverse if the below two conditions are met at the same time,
>                 1. The current insn_code doesn't exist or it's operand doesn't match,
>                    or the shift amount is beyond the half size of the machine mode;
>                 2. The reversed insn_code exists and it's operand matches.
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/zbb-rol-ror-04.c: New test.
>          * gcc.target/riscv/zbb-rol-ror-05.c: New test.
>          * gcc.target/riscv/zbb-rol-ror-06.c: New test.
>          * gcc.target/riscv/zbb-rol-ror-07.c: New test.
So I was waiting on test results to say this is ready for gcc-14 with 
some minor edits.  By the time those test results landed, gcc-14 has 
partially opened up.  Soo...

I updated various comments to hopefully make things clearer and adjusted 
the logic slightly in reverse_rotate_by_imm_p.

Bootstrapped and regression tested on riscv64.

Pushed to the trunk.

Jeff