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Wed, 10 Jan 2024 09:06:20 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 537DC20043; Wed, 10 Jan 2024 09:06:20 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 651D120040; Wed, 10 Jan 2024 09:06:18 +0000 (GMT) Received: from [9.197.240.105] (unknown [9.197.240.105]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 10 Jan 2024 09:06:18 +0000 (GMT) Message-ID: <21f8debe-c139-3dd1-1594-464684963692@linux.ibm.com> Date: Wed, 10 Jan 2024 17:06:16 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH] PR target/112886, Add %S to print_operand for vector pair support Content-Language: en-US To: Michael Meissner References: Cc: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Peter Bergner From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: NUAxefK2b5dK6qd6SVE-MDfojxvjv74O X-Proofpoint-ORIG-GUID: _ll0JRvgDJgmd5Z0_BFNm3nrGV7-fUL2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-10_02,2024-01-09_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401100074 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Mike, on 2024/1/6 06:18, Michael Meissner wrote: > In looking at support for load vector pair and store vector pair for the > PowerPC in GCC, I noticed that we were missing a print_operand output modifier > if you are dealing with vector pairs to print the 2nd register in the vector > pair. > > If the instruction inside of the asm used the Altivec encoding, then we could > use the %L modifier: It seems there is no Power specific documentation on operand modifiers like this "%L"? > > __vector_pair *p, *q, *r; > // ... > __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2" > : "=v" (*p) > : "v" (*q), "v" (*r)); > > Likewise if we know the value to be in a tradiational FPR register, %L will > work for instructions that use the VSX encoding: > > __vector_pair *p, *q, *r; > // ... > __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2" > : "=f" (*p) > : "f" (*q), "f" (*r)); > > But if have a value that is in a traditional Altivec register, and the > instruction uses the VSX encoding, %L will a value between 0 and 31, when it > should give a value between 32 and 63. > > This patch adds %S that acts like %x, except that it adds 1 to the > register number. Excepting for Peter's comments, since the existing "%L" has different handlings on REG_P and MEM_P: case 'L': /* Write second word of DImode or DFmode reference. Works on register or non-indexed memory only. */ if (REG_P (x)) fputs (reg_names[REGNO (x) + 1], file); else if (MEM_P (x)) ... , maybe we can extend the existing '%X' for this similarly (as it's capital of %x so easier to remember and it's only used for MEM_P now) instead of introducing a new "%S". But one argument can be a new character is more clear. Thoughts? BR, Kewen > > I have tested this on power10 and power9 little endian systems and on a power9 > big endian system. There were no regressions in the patch. Can I apply it to > the trunk? > > It would be nice if I could apply it to the open branches. Can I backport it > after a burn-in period? > > 2024-01-04 Michael Meissner > > gcc/ > > PR target/112886 > * config/rs6000/rs6000.cc (print_operand): Add %S output modifier. > * doc/md.texi (Modifiers): Mention %S can be used like %x. > > gcc/testsuite/ > > PR target/112886 > * /gcc.target/powerpc/pr112886.c: New test. > --- > gcc/config/rs6000/rs6000.cc | 10 +++++++--- > gcc/doc/md.texi | 5 +++-- > gcc/testsuite/gcc.target/powerpc/pr112886.c | 19 +++++++++++++++++++ > 3 files changed, 29 insertions(+), 5 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/powerpc/pr112886.c > > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index 5a7e00b03d1..ba89377c9ec 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -14504,13 +14504,17 @@ print_operand (FILE *file, rtx x, int code) > print_operand (file, x, 0); > return; > > + case 'S': > case 'x': > - /* X is a FPR or Altivec register used in a VSX context. */ > + /* X is a FPR or Altivec register used in a VSX context. %x prints > + the VSX register number, %S prints the 2nd register number for > + vector pair, decimal 128-bit floating and IBM 128-bit binary floating > + values. */ > if (!REG_P (x) || !VSX_REGNO_P (REGNO (x))) > - output_operand_lossage ("invalid %%x value"); > + output_operand_lossage ("invalid %%%c value", (code == 'S' ? 'S' : 'x')); > else > { > - int reg = REGNO (x); > + int reg = REGNO (x) + (code == 'S' ? 1 : 0); > int vsx_reg = (FP_REGNO_P (reg) > ? reg - 32 > : reg - FIRST_ALTIVEC_REGNO + 32); > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 47a87d6ceec..53ec957cb23 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -3386,8 +3386,9 @@ A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an > FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR > (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}). > > -When using @code{wa}, you should use the @code{%x} output modifier, so that > -the correct register number is printed. For example: > +When using @code{wa}, you should use either the @code{%x} or @code{%S} > +output modifier, so that the correct register number is printed. For > +example: > > @smallexample > asm ("xvadddp %x0,%x1,%x2" > diff --git a/gcc/testsuite/gcc.target/powerpc/pr112886.c b/gcc/testsuite/gcc.target/powerpc/pr112886.c > new file mode 100644 > index 00000000000..07196bdc220 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr112886.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target power10_ok } */ > +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ > + > +/* PR target/112886: Test that print_operand %S gives the correct register > + number for VSX registers (i.e. if the register is an Altivec register, the > + register number is 32..63 instead of 0..31. */ > + > +void > +test (__vector_pair *p, __vector_pair *q, __vector_pair *r) > +{ > + __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %S0,%S1,%S2" > + : "=v" (*p) > + : "v" (*q), "v" (*r)); > +} > + > +/* { dg-final { scan-assembler-times {\mxvadddp (3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3])\M} 2 } } */ > +/* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ > +/* { dg-final { scan-assembler-times {\mstxvp\M} 1 } } */