From: Eric Botcazou <ebotcazou@adacore.com>
To: David Edelsohn <dje.gcc@gmail.com>
Cc: gcc-patches@gcc.gnu.org,
Ramana Radhakrishnan <ramana.radhakrishnan@foss.arm.com>
Subject: Re: [PATCH] g++.dg/init/vbase1.C and g++.dg/cpp/ucn-1.C
Date: Mon, 16 Nov 2015 09:15:00 -0000 [thread overview]
Message-ID: <2230078.Wnj0yXVxZO@polaris> (raw)
In-Reply-To: <CAGWvnynxgVBDfUMKz5qYkjn42RgO8K+mdFSG0-Bmt_4AQ74ztQ@mail.gmail.com>
> No RISC architecture can store directly to MEM, so the expected RTL in
> g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
> probably should be disabled for ARM and other RISC architectures.
Some of them can store 0 directly to MEM though, for example SPARC.
--
Eric Botcazou
next prev parent reply other threads:[~2015-11-16 9:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-14 0:33 David Edelsohn
2015-11-14 1:01 ` Mike Stump
2015-11-14 10:16 ` Andreas Schwab
2015-11-14 13:09 ` David Edelsohn
2015-11-14 13:31 ` Jakub Jelinek
2015-11-14 13:36 ` David Edelsohn
2015-11-14 13:42 ` Andreas Schwab
2015-11-14 13:47 ` David Edelsohn
2015-11-16 9:15 ` Eric Botcazou [this message]
2015-11-16 13:29 ` David Edelsohn
2015-11-16 14:02 ` Renlin Li
2015-11-20 22:17 ` Mike Stump
2015-11-21 12:34 Uros Bizjak
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