From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by sourceware.org (Postfix) with ESMTPS id A2E593858C39 for ; Wed, 19 Jul 2023 09:45:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A2E593858C39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=adacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=adacore.com Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3143798f542so6879523f8f.2 for ; Wed, 19 Jul 2023 02:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore.com; s=google; t=1689759958; x=1692351958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CQxf5X+za4Jyqm6IQ33JGEsrQo+D4ZRyZXBipuaI/z4=; b=d1wM6WO1y2WDJ3D8c2ihfIRU5wCQ2zDr/+0cYMSBwjLr75MlqrAUhUdjNfR8D36i18 lHBIPKqxhzitkOznnQWXLCezxcvO7JWb+hPtfi30dSNsHFwNgDFGVe7BO5jhU/6crCXD 5nI5CC4AHtXyjk8NvVwkAcPEJ0+ByUR4SEobgSUxZhbp7vs/jbabTTdTEQ0NfooWoEUz JWTpggueiO9oJXrA2fvMn75cDg6gt3m5iGA5ZiZ7OSbbY84hLhxJPrnExgLtoRhUQ852 Qt6a9/AUD7cq1pUsZb/Isy1q2NrQSW6Z7GUqBstJ0cGo1JuPml26oHIOny278aR1HLeo TApQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689759958; x=1692351958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CQxf5X+za4Jyqm6IQ33JGEsrQo+D4ZRyZXBipuaI/z4=; b=EtvlDoXOSJwQPKB52R/s+LLvuxhlIuoeaTbgq0RLTi3oZqlZRZE8nvaK0c3Mz/eoc9 qVFW74ldFOe1Lvk0lQ7qxakyZkVt1KilGQmSaEMnTigLV1TwgchY4qA7+szvGDQ1VeDQ BYf2Sw6lQq9UmLArPheTvOgPkVpbbRpQt/ghCg99HEu8nVjguD8KblMUfwCgd2FPQFbL w2AjgrvFD5/8SzOczT8mOlupuo4yrdmShF/TjIwvOc3uwxz/rcBV1XsB+vQPK5Ze3GMs M5EbSEreBFHviZedSKn4P9YniJm2g+Dnym2uFx7pULmjnAVL8PGz9tbgaXkj7bqWy3U2 mgSw== X-Gm-Message-State: ABy/qLa+tr9Cc1Uw8QP7Hs5PCqcImzLRkSQrVf+OWKC3nvQtCztyoS4i JWZtzEfG0H0GWn503o+lOB6HpQ== X-Google-Smtp-Source: APBJJlGpGMX3cJ+axF0axawlz6IA8FEtNrAYnRT+6+rKDw1fIeqb3v8UKDPGpZP0ZZD07DcSatnwbA== X-Received: by 2002:adf:f30a:0:b0:313:dfb8:b4d0 with SMTP id i10-20020adff30a000000b00313dfb8b4d0mr15360064wro.66.1689759957999; Wed, 19 Jul 2023 02:45:57 -0700 (PDT) Received: from arcturus.localnet ([2a01:cb10:8647:7500:e04b:d5ba:7d93:b19c]) by smtp.gmail.com with ESMTPSA id h12-20020adff4cc000000b0031411b7087dsm4843280wrp.20.2023.07.19.02.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 02:45:57 -0700 (PDT) From: Eric Botcazou X-Google-Original-From: Eric Botcazou To: Richard Biener Cc: YunQiang Su , gcc-patches@gcc.gnu.org, YunQiang Su , gcc-patches@gcc.gnu.org, pinskia@gmail.com, jeffreyalaw@gmail.com, ian@airs.com Subject: Re: [PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible Date: Wed, 19 Jul 2023 11:45:56 +0200 Message-ID: <2289802.ElGaqSPkdT@arcturus> In-Reply-To: References: <20230719041639.2967597-1-yunqiang.su@cipunited.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > I don't see that. That's definitely not what GCC expects here, > the left-most word of the doubleword should be unchanged. > > Your testcase should be a dg-do-run and probably more like > > NOMIPS16 int __attribute__((noipa)) test (const unsigned char *buf) > { > int val; > ((unsigned char*)&val)[0] = *buf++; > ((unsigned char*)&val)[1] = *buf++; > ((unsigned char*)&val)[2] = *buf++; > ((unsigned char*)&val)[3] = *buf++; > return val; > } > int main() > { > int val = 0x01020304; > val = test (&val); > if (val != 0x01020304) > abort (); > } > > not sure if I got endianess correct. Now, the question is what > WORD_REGISTER_OPERATIONS implies for a bitfield insert and what > the MIPS ABI says for returning SImode. WORD_REGISTER_OPERATIONS must *not* be taken account for bit-fields, see e;g. word_register_operation_p: /* Return true if X is an operation that always operates on the full registers for WORD_REGISTER_OPERATIONS architectures. */ inline bool word_register_operation_p (const_rtx x) { switch (GET_CODE (x)) { case CONST_INT: case ROTATE: case ROTATERT: case SIGN_EXTRACT: case ZERO_EXTRACT: return false; default: return true; } } -- Eric Botcazou