From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27789 invoked by alias); 23 Oct 2019 09:43:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 27724 invoked by uid 89); 23 Oct 2019 09:43:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=launched, vmx, vwa X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Oct 2019 09:42:58 +0000 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9N9gBpv058615 for ; Wed, 23 Oct 2019 05:42:56 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vtkq09tgc-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 05:42:55 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 10:42:50 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9N9gG4229032882 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 09:42:16 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9A30811C04A; Wed, 23 Oct 2019 09:42:48 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2028E11C050; Wed, 23 Oct 2019 09:42:47 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.149]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 09:42:46 +0000 (GMT) Subject: [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff unit size From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Date: Wed, 23 Oct 2019 10:15:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Content-Type: multipart/mixed; boundary="------------CBF94C89DD2A57588F27D2E1" x-cbid: 19102309-0020-0000-0000-0000037D0250 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102309-0021-0000-0000-000021D342FE Message-Id: <22fd6de1-dc31-a977-a803-0a2cb3f11444@linux.ibm.com> X-IsSubscribed: yes X-SW-Source: 2019-10/txt/msg01631.txt.bz2 This is a multi-part message in MIME format. --------------CBF94C89DD2A57588F27D2E1 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 7bit Content-length: 1367 Hi, Following the previous one 2/3, this patch is to update the vector conversions between fixed point and floating point with different element unit sizes, such as: SP <-> DI, DP <-> SI. Bootstrap and regression testing just launched. gcc/ChangeLog 2019-10-23 Kewen Lin * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes. * config/rs6000/vsx.md (UNSPEC_VSX_CVDPSXWS, UNSPEC_VSX_CVSXDSP, UNSPEC_VSX_CVUXDSP, UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove. (vsx_xvcvspdp): New define_expand, old one split to... (vsx_xvcvspdp_be): ... this. New. And... (vsx_xvcvspdp_le): ... this. New. (vsx_xvcvdpsp): New define_expand, old one split to... (vsx_xvcvdpsp_be): ... this. New. And... (vsx_xvcvdpsp_le): ... this. New. (vsx_xvcvdp[su]xws): New define_expand, old one split to... (vsx_xvcvdpxws_be): ... this. New. And... (vsx_xvcvdpxws_le): ... this. New. (vsx_xvcv[su]xdsp): New define_expand, old one split to... (vsx_xvcvxdsp_be): ... this. New. And... (vsx_xvcvxdsp_le): ... this. New. (vsx_xvcv[su]xwdp): New define_expand, old one split to... (vsx_xvcvxwdp_be): ... this. New. And... (vsx_xvcvxwdp_le): ... this. New. (vsx_xvcvsp[su]xds): New define_expand, old one split to... (vsx_xvcvspxds_be): ... this. New. And... (vsx_xvcvspxds_le): ... this. New. --------------CBF94C89DD2A57588F27D2E1 Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="0003.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0003.patch" Content-length: 12169 >From 5315810c391b75661de9027ea2848d31390e1d8b Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 23 Oct 2019 04:02:00 -0500 Subject: [PATCH 3/3] Update RTL pattern on vector fp/int 32bit <-> 64bit conversion --- gcc/config/rs6000/rs6000-modes.def | 4 + gcc/config/rs6000/vsx.md | 240 +++++++++++++++++++++++++++---------- 2 files changed, 181 insertions(+), 63 deletions(-) diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 677062c..449e176 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +/* Half VMX/VSX vector (for select) */ +VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ +VECTOR_MODE (INT, SI, 2); /* V2SI */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 83e4071..44025f6 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -265,7 +265,6 @@ ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT - UNSPEC_VSX_CVDPSXWS UNSPEC_VSX_CVDPUXWS UNSPEC_VSX_CVSPDP UNSPEC_VSX_CVHPSP @@ -273,10 +272,6 @@ UNSPEC_VSX_CVDPSPN UNSPEC_VSX_CVSXWDP UNSPEC_VSX_CVUXWDP - UNSPEC_VSX_CVSXDSP - UNSPEC_VSX_CVUXDSP - UNSPEC_VSX_CVSPSXDS - UNSPEC_VSX_CVSPUXDS UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -2106,22 +2101,69 @@ "xscvdpsp %x0,%x1" [(set_attr "type" "fp")]) -(define_insn "vsx_xvcvspdp" +(define_insn "vsx_xvcvspdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvspdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" "xvcvspdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvdpsp" +(define_expand "vsx_xvcvspdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1])); + DONE; +}) + +(define_insn "vsx_xvcvdpsp_be" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") - (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" + (float_truncate:V4SF + (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa") + (vec_select:V2DF (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" "xvcvdpsp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_insn "vsx_xvcvdpsp_le" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") + (float_truncate:V4SF + (vec_concat:V4DF + (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvdpsp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpsp" + [(match_operand:V4SF 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvdpsp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvdpsp_le (operands[0], operands[1])); + DONE; +}) + ;; xscvspdp, represent the scalar SF type as V4SF (define_insn "vsx_xscvspdp" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") @@ -2301,48 +2343,144 @@ ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. -(define_insn "vsx_xvcvdpsxws" +;; Convert vector of 64-bit floating point numbers to vector of +;; 32-bit signed/unsigned integers. +(define_insn "vsx_xvcvdpxws_be" [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa") - (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVDPSXWS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpsxws %x0,%x1" + (any_fix:V4SI + (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa") + (vec_select:V2DF (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvdpxws %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvdpuxws" +(define_insn "vsx_xvcvdpxws_le" [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa") - (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVDPUXWS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpuxws %x0,%x1" + (any_fix:V4SI + (vec_concat:V4DF + (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvdpxws %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvsxdsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXDSP))] +(define_expand "vsx_xvcvdpxws" + [(match_operand:V4SI 0 "vsx_register_operand") + (match_operand:V2DF 1 "vsx_register_operand") + (any_fix (pc))] "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxdsp %x0,%x1" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvdpxws_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvdpxws_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 64-bit signed/unsigned integers to vector of +;; 32-bit floating point numbers. +(define_insn "vsx_xvcvxdsp_be" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (any_float:V4SF + (vec_concat:V4DI (match_operand:V2DI 1 "vsx_register_operand" "wa") + (vec_select:V2DI (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvxdsp %x0,%x1" [(set_attr "type" "vecfloat")]) -(define_insn "vsx_xvcvuxdsp" +(define_insn "vsx_xvcvxdsp_le" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXDSP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxdsp %x0,%x1" + (any_float:V4SF + (vec_concat:V4DI + (vec_select:V2DI (match_operand:V2DI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 0)])) + (match_dup 1))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" + "xvcvxdsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_expand "vsx_xvcvxdsp" + [(match_operand:V4SF 0 "vsx_register_operand") + (match_operand:V2DI 1 "vsx_register_operand") + (any_float (pc))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxdsp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxdsp_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 32-bit signed/unsigned integers to vector of +;; 64-bit floating point numbers. +(define_insn "vsx_xvcvxwdp_be" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -;; Convert from 32-bit to 64-bit types -;; Provide both vector and scalar targets -(define_insn "vsx_xvcvsxwdp" +(define_insn "vsx_xvcvxwdp_le" [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWDP))] + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvxwdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SI 1 "vsx_register_operand") + (any_float (pc))] "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxwdp %x0,%x1" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxwdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxwdp_le (operands[0], operands[1])); + DONE; +}) + +;; Convert vector of 32-bit floating point numbers to vector of +;; 64-bit signed/unsigned integers. +(define_insn "vsx_xvcvspxds_be" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspxds_le" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspxds" + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand") + (any_fix (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspxds_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspxds_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvsxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2351,14 +2489,6 @@ "xvcvsxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvuxwdp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxwdp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_insn "vsx_xvcvuxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2367,22 +2497,6 @@ "xvcvuxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspsxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspsxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - -(define_insn "vsx_xvcvspuxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspuxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df" -- 2.7.4 --------------CBF94C89DD2A57588F27D2E1--