From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 614383858D28; Sun, 7 May 2023 11:34:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 614383858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 347BAGus006066; Sun, 7 May 2023 11:34:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=date : from : to : cc : subject : in-reply-to : references : message-id : content-type : content-transfer-encoding : mime-version; s=pp1; bh=oYfkCeUsmYKZh+XfX1oIlQtOuoPs+ApNtC710TKifZw=; b=Z85JsL7+BJqrPw4l2a2zuUBQur3Jz3khgaqVoZRWRj1qcKR1I37SL383wzfOnu43//nG tgl530h4fFYPsq805cGWRg6wtyik2YNbtoZCq2hc7LKEKypaVwecb4CQpqPWizP9bfHf 5iePubmu6urIL0NDQP0baL1+DMOdk+rPJMhyYdnN+JyEOCYUsqE2qPulMuZa9+IZf82l 09BjkUE8Y7yU2SwIZhz0RG5YXL4S9XbkfqEmTrljWvJPhXawIBzdFtQ2cE5cMeU4ITQj PCMMby2MKNuSEbd+R5Z/le80uYcMSkLX6vY0lcWVppTeTSYunB6vYI9ao3s2RsGjuuCF 3Q== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qdka0fbsx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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Sun, 7 May 2023 11:34:53 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 727A958056; Sun, 7 May 2023 11:34:53 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1A29758052; Sun, 7 May 2023 11:34:53 +0000 (GMT) Received: from ltc.linux.ibm.com (unknown [9.5.196.140]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Sun, 7 May 2023 11:34:53 +0000 (GMT) Date: Sun, 07 May 2023 19:34:52 +0800 From: guojiufu To: "Kewen.Lin" Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, gcc-patches@gcc.gnu.org Subject: Re: [PATCH V3] rs6000: Load high and low part of 64bit constant independently In-Reply-To: References: <20230104065140.91578-1-guojiufu@linux.ibm.com> Message-ID: <231174f259f9db3c4378a9ba29d7fba4@linux.ibm.com> X-Sender: guojiufu@linux.ibm.com Content-Type: text/plain; charset=US-ASCII; format=flowed X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 0ylkBiFkjyKEO5LSebsP9ICD2fQpiXS8 X-Proofpoint-ORIG-GUID: 0J7GxOCuedE9ac6tfrpcCyieVvmDQZvj Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-07_06,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305070089 X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, On 2023-04-26 17:35, Kewen.Lin wrote: > Hi Jeff, > > on 2023/1/4 14:51, Jiufu Guo wrote: >> Hi, >> >> Compare with previous version, this patch updates the comments only. >> https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html >> >> For a complicate 64bit constant, below is one instruction-sequence to >> build: >> lis 9,0x800a >> ori 9,9,0xabcd >> sldi 9,9,32 >> oris 9,9,0xc167 >> ori 9,9,0xfa16 >> >> while we can also use below sequence to build: >> lis 9,0xc167 >> lis 10,0x800a >> ori 9,9,0xfa16 >> ori 10,10,0xabcd >> rldimi 9,10,32,0 >> This sequence is using 2 registers to build high and low part firstly, >> and then merge them. >> >> In parallel aspect, this sequence would be faster. (Ofcause, using 1 >> more >> register with potential register pressure). >> >> The instruction sequence with two registers for parallel version can >> be >> generated only if can_create_pseudo_p. Otherwise, the one register >> sequence is generated. >> >> Bootstrap and regtest pass on ppc64{,le}. >> Is this ok for trunk? > > OK for trunk, thanks for the improvement! Thanks! Committed via r14-555-gb05b529125fa51. BR, Jeff (Jiufu) > > BR, > Kewen > >> >> >> BR, >> Jeff(Jiufu) >> >> >> gcc/ChangeLog: >> >> * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate >> more parallel code if can_create_pseudo_p. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/powerpc/parall_5insn_const.c: New test. >>