From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25391 invoked by alias); 1 Sep 2014 19:56:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 25380 invoked by uid 89); 1 Sep 2014 19:56:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 01 Sep 2014 19:56:50 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s81JrKUV021239; Mon, 1 Sep 2014 12:53:20 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s81JrK4N021121; Mon, 1 Sep 2014 12:53:20 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 3/4] rs6000: Merge zero_extend*si2 and zero_extend*di2 Date: Mon, 01 Sep 2014 19:56:00 -0000 Message-Id: <2410ee9eef400b38ffbeb28686e61ad2658de2bd.1409581755.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg00073.txt.bz2 Don't group the insns based on extended size; use source size instead. Use the "andi." insn rather than "rldicl." and friends if possible. The instructions guarded by TARGET_LFIWZX do not need that guard: the constraints already guarantee the (correct!) condition. Tested as usual; no regressions. Okay to apply? Segher 2014-09-01 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (QHSI): Delete. (EXTQI, EXTHI, EXTSI): New mode iterators. (zero_extenddi2, *zero_extenddi2_internal1, *zero_extenddi2_internal2, *zero_extenddi2_internal3, *zero_extendsidi2_lfiwzx, zero_extendqisi2, zero_extendhisi2, 9 anonymous instructions, and 8 splitters): Delete. (zero_extendqi2, *zero_extendqi2_dot, *zero_extendqi2_dot2, zero_extendhi2, *zero_extendhi2_dot, *zero_extendhi2_dot2, zero_extendsi2, *zero_extendsi2_dot, *zero_extendsi2_dot2): New. --- gcc/config/rs6000/rs6000.md | 379 +++++++++++++++----------------------------- 1 file changed, 131 insertions(+), 248 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f9e1eba..6cd6404 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -309,8 +309,14 @@ (define_mode_iterator INT [QI HI SI DI TI PTI]) ; Any supported integer mode that fits in one register. (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) -; extend modes for DImode -(define_mode_iterator QHSI [QI HI SI]) +; Everything we can extend QImode to. +(define_mode_iterator EXTQI [HI SI (DI "TARGET_POWERPC64")]) + +; Everything we can extend HImode to. +(define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")]) + +; Everything we can extend SImode to. +(define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")]) ; QImode or HImode for small atomic ops (define_mode_iterator QHI [QI HI]) @@ -564,79 +570,112 @@ (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v") ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. -(define_expand "zero_extenddi2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))] - "TARGET_POWERPC64" - "") - -(define_insn "*zero_extenddi2_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] - "TARGET_POWERPC64 && (mode != SImode || !TARGET_LFIWZX)" +(define_insn "zero_extendqi2" + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] + "" "@ - lz%U1%X1 %0,%1 - rldicl %0,%1,0," + lbz%U1%X1 %0,%1 + rlwinm %0,%1,0,0xff" [(set_attr "type" "load,shift")]) -(define_insn "*zero_extenddi2_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) +(define_insn_and_split "*zero_extendqi2_dot" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:DI 2 "=r,r"))] - "TARGET_64BIT" + (clobber (match_scratch:EXTQI 0 "=r,r"))] + "rs6000_gen_cell_microcode" "@ - rldicl. %2,%1,0, + andi. %0,%1,0xff #" - [(set_attr "type" "shift") + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) +(define_insn_and_split "*zero_extendqi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) + (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTQI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + andi. %0,%1,0xff + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTQI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + + +(define_insn "zero_extendhi2" + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] + "" + "@ + lhz%U1%X1 %0,%1 + rlwinm %0,%1,0,0xffff" + [(set_attr "type" "load,shift")]) -(define_insn "*zero_extenddi2_internal3" +(define_insn_and_split "*zero_extendhi2_dot" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) + (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI (match_dup 1)))] - "TARGET_64BIT" + (clobber (match_scratch:EXTHI 0 "=r,r"))] + "rs6000_gen_cell_microcode" "@ - rldicl. %0,%1,0, + andi. %0,%1,0xffff #" - [(set_attr "type" "shift") + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTHI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) +(define_insn_and_split "*zero_extendhi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (zero_extend:DI (match_dup 1)))] - "TARGET_POWERPC64 && reload_completed" + (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTHI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + andi. %0,%1,0xffff + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" [(set (match_dup 0) - (zero_extend:DI (match_dup 1))) + (zero_extend:EXTHI (match_dup 1))) (set (match_dup 2) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) -(define_insn "*zero_extendsidi2_lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") - (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] - "TARGET_POWERPC64 && TARGET_LFIWZX" + +(define_insn "zero_extendsi2" + [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") + (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] + "" "@ lwz%U1%X1 %0,%1 rldicl %0,%1,0,32 @@ -645,6 +684,48 @@ (define_insn "*zero_extendsidi2_lfiwzx" lxsiwzx %x0,%y1" [(set_attr "type" "load,shift,mffgpr,fpload,fpload")]) +(define_insn_and_split "*zero_extendsi2_dot" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:EXTSI 0 "=r,r"))] + "rs6000_gen_cell_microcode" + "@ + rldicl. %0,%1,0,32 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:DI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + +(define_insn_and_split "*zero_extendsi2_dot2" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r") + (zero_extend:EXTSI (match_dup 1)))] + "rs6000_gen_cell_microcode" + "@ + rldicl. %0,%1,0,32 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)" + [(set (match_dup 0) + (zero_extend:EXTSI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + + (define_insn "extendqidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] @@ -867,74 +948,6 @@ (define_split (const_int 0)))] "") -(define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lbz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "extendqisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -995,68 +1008,6 @@ (define_split (const_int 0)))] "") -(define_insn "" - [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lbz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:HI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:HI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:HI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") - (zero_extend:HI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "gpc_reg_operand" "") - (zero_extend:HI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:HI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "extendqihi2" [(set (match_operand:HI 0 "gpc_reg_operand" "=r") @@ -1117,74 +1068,6 @@ (define_split (const_int 0)))] "") -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] - "" - "") - -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "" - "@ - lhz%U1%X1 %0,%1 - rlwinm %0,%1,0,0xffff" - [(set_attr "type" "load,shift")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 2 "=r,r"))] - "" - "@ - andi. %2,%1,0xffff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 2 ""))] - "reload_completed" - [(set (match_dup 2) - (zero_extend:SI (match_dup 1))) - (set (match_dup 0) - (compare:CC (match_dup 2) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (zero_extend:SI (match_dup 1)))] - "" - "@ - andi. %0,%1,0xffff - #" - [(set_attr "type" "logical,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (zero_extend:SI (match_dup 1)))] - "reload_completed" - [(set (match_dup 0) - (zero_extend:SI (match_dup 1))) - (set (match_dup 2) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_expand "extendhisi2" [(set (match_operand:SI 0 "gpc_reg_operand" "") -- 1.8.1.4