From: Dennis Zhang <Dennis.Zhang@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
nd <nd@arm.com>, Richard Earnshaw <Richard.Earnshaw@arm.com>,
James Greenhalgh <James.Greenhalgh@arm.com>,
Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Richard Sandiford <Richard.Sandiford@arm.com>
Subject: Re: [PATCH][AArch64] Enable CLI for Armv8.6-a: armv8.6-a, i8mm and bf16
Date: Thu, 05 Dec 2019 15:31:00 -0000 [thread overview]
Message-ID: <246f80da-367a-ea69-645a-19c0c684e404@arm.com> (raw)
In-Reply-To: <mpt8snyx2g6.fsf@arm.com>
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Hi Richard,
On 29/11/2019 13:00, Richard Sandiford wrote:
> Hi Dennis,
>
> Sorry for the slow response.
>
> Dennis Zhang <Dennis.Zhang@arm.com> writes:
>> Hi all,
>>
>> This patch is part of a series adding support for Armv8.6-A features.
>> It enables options including -march=armv8.6-a, +i8mm and +bf16.
>> The +i8mm and +bf16 features are mandatory for Armv8.6-a and optional
>> for Armv8.2-a and onward.
>> Documents are at https://developer.arm.com/docs/ddi0596/latest
>>
>> Regtested for aarch64-none-linux-gnu.
>>
>> Please help to check if it's ready for trunk.
>>
>> Many thanks!
>> Dennis
>>
>> gcc/ChangeLog:
>>
>> 2019-11-26 Dennis Zhang <dennis.zhang@arm.com>
>>
>> * config/aarch64/aarch64-arches.def (armv8.6-a): New.
>> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
>> __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and
>> __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled.
>> * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New.
>> * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro.
>> (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise.
>> (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise.
>> (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
>> * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2019-11-26 Dennis Zhang <dennis.zhang@arm.com>
>>
>> * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm
>> and bf16 features.
>>
>> diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def
>> index d258bd49244..e464d329c1a 100644
>> --- a/gcc/config/aarch64/aarch64-arches.def
>> +++ b/gcc/config/aarch64/aarch64-arches.def
>> @@ -36,5 +36,6 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2)
>> AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3)
>> AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4)
>> AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5)
>> +AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6)
>>
>> #undef AARCH64_ARCH
>> diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
>> index f3da07fd28a..20d1e00552b 100644
>> --- a/gcc/config/aarch64/aarch64-c.c
>> +++ b/gcc/config/aarch64/aarch64-c.c
>> @@ -165,6 +165,12 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
>> aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
>> aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
>>
>> + aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
>> + aarch64_def_or_undef (TARGET_BF16_SIMD,
>> + "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
>> + aarch64_def_or_undef (TARGET_BF16_FP,
>> + "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
>> +
>> /* Not for ACLE, but required to keep "float.h" correct if we switch
>> target between implementations that do or do not support ARMv8.2-A
>> 16-bit floating-point extensions. */
>> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
>> index d3ae1b2431b..5b7c3b8a213 100644
>> --- a/gcc/config/aarch64/aarch64-option-extensions.def
>> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
>> @@ -198,4 +198,14 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD |
>> /* Enabling or disabling "tme" only changes "tme". */
>> AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
>>
>> +/* Enabling "i8mm" also enables "simd".
>> + Disabling "i8mm" only disables "i8mm". */
>> +AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, AARCH64_FL_SIMD, \
>> + 0, false, "i8mm")
>
> We have to maintain the transitive closure of features by hand,
> so anything that enables AARCH64_FL_SIMD also needs to enable
> AARCH64_FL_FP.
>
> We should also add i8mm to the list of things that +nosimd and +nofp
> disable.
>
> (It would be better to do this automatically, but that's future work.)
>
>> +/* Enabling "bf16" also enables "simd" and "fp".
>> + Disabling "bf16" only disables "bf16". */
>> +AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, AARCH64_FL_SIMD | AARCH64_FL_FP,
>> + 0, false, "bf16")
>
> Similarly here we should add bf16 to the list of things that +nofp disables.
>
>> @@ -308,6 +323,13 @@ extern unsigned aarch64_architecture_version;
>> /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
>> #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG)
>>
>> +/* I8MM instructions are enabled through +i8mm. */
>> +#define TARGET_I8MM (TARGET_SIMD && AARCH64_ISA_I8MM)
>
> This should then just be AARCH64_ISA_I8MM (i.e. no need to test
> TARGET_SIMD).
>
>> +
>> +/* BF16 instructions are enabled through +bf16. */
>> +#define TARGET_BF16_FP (AARCH64_ISA_BF16 && TARGET_FLOAT)
>
> Similarly here we don't need a test for TARGET_FLOAT.
>
The updated patch has added fp to i8mm 'also enable' list.
And i8mm and bf16 are added to the disabling lists of nofp and nosimd.
Also removed unnecessary checking of flags.
>> +#define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
>> +
>> /* Make sure this is always defined so we don't have to check for ifdefs
>> but rather use normal ifs. */
>> #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
>> index 403be47d893..30647e52c07 100644
>> --- a/gcc/doc/invoke.texi
>> +++ b/gcc/doc/invoke.texi
>> @@ -16045,7 +16045,10 @@ more feature modifiers. This option has the form
>>
>> The permissible values for @var{arch} are @samp{armv8-a},
>> @samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a},
>> -@samp{armv8.5-a} or @var{native}.
>> +@samp{armv8.5-a}, @samp{armv8.6-a} or @var{native}.
>> +
>> +The value @samp{armv8.6-a} implies @samp{armv8.5-a} and enables compiler
>> +support for the ARMv8.6-A architecture extensions.
>
> This then goes on to:
>
> -----------------------------------------------------------------
> The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler
> support for the ARMv8.5-A architecture extensions.
>
> The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler
> support for the ARMv8.4-A architecture extensions.
>
> The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler
> support for the ARMv8.3-A architecture extensions.
>
> The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
> support for the ARMv8.2-A architecture extensions.
>
> The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
> support for the ARMv8.1-A architecture extension. In particular, it
> enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features.
> -----------------------------------------------------------------
>
> I don't think we'd have written it like this if we'd been developing
> and submitting Armv8-A to Armv8.6-A (or Armv8.5-A) all in one go.
> It's just kind of grown by copying what Armv8.(x-1)-A did.
>
> How about replacing "The permissible values..." onwards with something like:
>
> -----------------------------------------------------------------
> The table below summarizes the permissable values for @var{arch}
> and the features that they enable by default:
>
> @multitable @columnfractions .25 .25 .50
> @headitem @var{arch} value @tab Architecture @tab Includes by default
> ...
> @item @samp{armv8.6-a} @tab Armv8.6
> @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
> @end multitable
> -----------------------------------------------------------------
>
> (Completely untested.)
>
> Or we could put "armv8.5-a" and "bf16, i8mm" (with or without "+"s)
> into separate columns, perhaps "Extends" and "Includes by default".
>
> (Any of those options would be fine with me FWIW.)
>
This part is modified according to your comment.
Thanks for the detailed suggestions.
>> @@ -16276,6 +16279,7 @@ generation. This option is enabled by default for @option{-march=armv8.5-a}.
>> Enable the Armv8-a Execution and Data Prediction Restriction instructions.
>> This option is only to enable the extension at the assembler level and does
>> not affect code generation. This option is enabled by default for
>> +@option{-march=armv8.5-a}.
>> @item sve2
>> Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
>> instructions.
>> @@ -16287,9 +16291,18 @@ Enable SVE2 sm4 instructions. This also enables SVE2 instructions.
>> Enable SVE2 aes instructions. This also enables SVE2 instructions.
>> @item sve2-sha3
>> Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
>> -@option{-march=armv8.5-a}.
>> @item tme
>> Enable the Transactional Memory Extension.
>> +@item i8mm
>> +Enable 8-bit Integer Matrix Multiply instructions. This also enables
>> +Advanced SIMD instructions. This option is enabled by default for
>
> After the above: "Advanced SIMD and floating-point"
>
>> +@option{-march=armv8.6-a}. Use of this option with architectures prior to
>> +Armv8.2-A is not supported.
>> +@item bf16
>> +Enable brain half-precision floating-point instructions. This also enables
>> +Advanced SIMD and floating-point instructions. This option is enabled by
>> +default for @option{-march=armv8.6-a}. Use of this option with architectures
>> +prior to Armv8.2-A is not supported.
>>
>> @end table
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
>> index 608b89d19ce..2983e271114 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
>> @@ -13,6 +13,59 @@
>> #error "__ARM_FEATURE_TME is defined but should not be!"
>> #endif
>>
>> +#pragma GCC push_options
>> +#pragma GCC target ("arch=armv8.6-a")
>> +#ifndef __ARM_FEATURE_MATMUL_INT8
>> +#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
>> +#endif
>> +#pragma GCC pop_options
>> +
>> +#pragma GCC push_options
>> +#pragma GCC target ("arch=armv8.2-a+i8mm")
>> +#ifndef __ARM_FEATURE_MATMUL_INT8
>> +#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
>> +#endif
>> +#pragma GCC pop_options
>> +
>> +#ifdef __ARM_FEATURE_MATMUL_INT8
>> +#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
>> +#endif
>
> Not your bug, but we should start the file with:
>
> #pragma GCC target ("arch=armv8-a")
>
> otherwise anyone running the testsuite with -march=armv8.6-a will
> get failures here.
>
>> +
>> +#pragma GCC push_options
>> +#pragma GCC target ("arch=armv8.6-a")
>> +#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
>> +#endif
>> +#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
>> +#endif
>> +#pragma GCC pop_options
>> +
>> +#pragma GCC push_options
>> +#pragma GCC target ("arch=armv8.2-a+bf16")
>> +#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
>> +#endif
>> +#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
>> +#endif
>> +#pragma GCC pop_options
>> +
>> +#pragma GCC push_options
>> +#pragma GCC target ("arch=armv8.2-a+bf16+nosimd")
>> +#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
>> +#endif
>> +#pragma GCC pop_options
>> +
>
> For completeness, we might as well test __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
> is defined.
>
>> +#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is defined but should not be!"
>> +#endif
>> +
>> +#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
>> +#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
>> +#endif
>
> Very, very minor, but since the others have no blank line between the
> two tests, I think it'd be more consistent not to have one here either.
>
The tests are updated with several new cases to show nofp and nosimd
working properly for i8mm and bf16.
Finally, the ChangeLog is updated as following:
gcc/ChangeLog:
2019-12-04 Dennis Zhang <dennis.zhang@arm.com>
* config/aarch64/aarch64-arches.def (armv8.6-a): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and
__ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled.
* config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New.
(fp): Disabling fp also disables i8mm and bf16.
(simd): Disabling simd also disables i8mm.
* config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro.
(AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise.
(AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise.
(TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
* doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options. Add
a new table to list permissible values for ARCH.
gcc/testsuite/ChangeLog:
2019-12-04 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm
and bf16 features.
Many thanks!
Dennis
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diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def
index d258bd49244..e464d329c1a 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -36,5 +36,6 @@ AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2)
AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3)
AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4)
AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5)
+AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6)
#undef AARCH64_ARCH
diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index f3da07fd28a..20d1e00552b 100644
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -165,6 +165,12 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
+ aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
+ aarch64_def_or_undef (TARGET_BF16_SIMD,
+ "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
+ aarch64_def_or_undef (TARGET_BF16_FP,
+ "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
+
/* Not for ACLE, but required to keep "float.h" correct if we switch
target between implementations that do or do not support ARMv8.2-A
16-bit floating-point extensions. */
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index d3ae1b2431b..52c0fb79f82 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -52,25 +52,27 @@
/* Enabling "fp" just enables "fp".
Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
- "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
- "sve2-bitperm". */
+ "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
+ "sve2-bitperm", "i8mm" and "bf16". */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
- AARCH64_FL_SVE2_BITPERM, false, "fp")
+ AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
+ AARCH64_FL_BF16, false, "fp")
/* Enabling "simd" also enables "fp".
Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
- "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
- "sve2-bitperm". */
+ "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
+ "sve2-bitperm", and "i8mm". */
AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
- AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
+ AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
+ AARCH64_FL_I8MM, false, \
"asimd")
/* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
@@ -198,4 +200,14 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD |
/* Enabling or disabling "tme" only changes "tme". */
AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
+/* Enabling "i8mm" also enables "simd" and "fp".
+ Disabling "i8mm" only disables "i8mm". */
+AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, \
+ AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "i8mm")
+
+/* Enabling "bf16" also enables "simd" and "fp".
+ Disabling "bf16" only disables "bf16". */
+AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \
+ AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "bf16")
+
#undef AARCH64_OPT_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index ee01909abb9..1408e7989b6 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -202,6 +202,15 @@ extern unsigned aarch64_architecture_version;
/* Transactional Memory Extension. */
#define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */
+/* Armv8.6-A architecture extensions. */
+#define AARCH64_FL_V8_6 (1ULL << 34)
+
+/* 8-bit Integer Matrix Multiply (I8MM) extensions. */
+#define AARCH64_FL_I8MM (1ULL << 35)
+
+/* Brain half-precision floating-point (BFloat16) Extension. */
+#define AARCH64_FL_BF16 (1ULL << 36)
+
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
@@ -223,6 +232,9 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_FL_FOR_ARCH8_5 \
(AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \
| AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES)
+#define AARCH64_FL_FOR_ARCH8_6 \
+ (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \
+ | AARCH64_FL_I8MM | AARCH64_FL_BF16)
/* Macros to test ISA flags. */
@@ -249,6 +261,9 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5)
#define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)
#define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG)
+#define AARCH64_ISA_V8_6 (aarch64_isa_flags & AARCH64_FL_V8_6)
+#define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM)
+#define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
@@ -308,6 +323,13 @@ extern unsigned aarch64_architecture_version;
/* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
#define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG)
+/* I8MM instructions are enabled through +i8mm. */
+#define TARGET_I8MM (AARCH64_ISA_I8MM)
+
+/* BF16 instructions are enabled through +bf16. */
+#define TARGET_BF16_FP (AARCH64_ISA_BF16)
+#define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
+
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d165f31a865..1192e8f4b06 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16050,25 +16050,22 @@ Specify the name of the target architecture and, optionally, one or
more feature modifiers. This option has the form
@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
-The permissible values for @var{arch} are @samp{armv8-a},
-@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a},
-@samp{armv8.5-a} or @var{native}.
-
-The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler
-support for the ARMv8.5-A architecture extensions.
-
-The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler
-support for the ARMv8.4-A architecture extensions.
-
-The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler
-support for the ARMv8.3-A architecture extensions.
-
-The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
-support for the ARMv8.2-A architecture extensions.
-
-The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
-support for the ARMv8.1-A architecture extension. In particular, it
-enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features.
+The table below summarizes the permissible values for @var{arch}
+and the features that they enable by default:
+
+@multitable @columnfractions 0.20 0.20 0.60
+@headitem @var{arch} value @tab Architecture @tab Includes by default
+@item @samp{armv8.1-a} @tab Armv8.1-A
+@tab @samp{armv8-a}, @samp{+crc}, @samp{+lse}, @samp{+rdma}
+@item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a}
+@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
+@item @samp{armv8.4-a} @tab Armv8.4-A
+@tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
+@item @samp{armv8.5-a} @tab Armv8.5-A
+@tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
+@item @samp{armv8.6-a} @tab Armv8.6-A
+@tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
+@end multitable
The value @samp{native} is available on native AArch64 GNU/Linux and
causes the compiler to pick the architecture of the host system. This
@@ -16283,6 +16280,7 @@ generation. This option is enabled by default for @option{-march=armv8.5-a}.
Enable the Armv8-a Execution and Data Prediction Restriction instructions.
This option is only to enable the extension at the assembler level and does
not affect code generation. This option is enabled by default for
+@option{-march=armv8.5-a}.
@item sve2
Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
instructions.
@@ -16294,9 +16292,18 @@ Enable SVE2 sm4 instructions. This also enables SVE2 instructions.
Enable SVE2 aes instructions. This also enables SVE2 instructions.
@item sve2-sha3
Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
-@option{-march=armv8.5-a}.
@item tme
Enable the Transactional Memory Extension.
+@item i8mm
+Enable 8-bit Integer Matrix Multiply instructions. This also enables
+Advanced SIMD and floating-point instructions. This option is enabled by
+default for @option{-march=armv8.6-a}. Use of this option with architectures
+prior to Armv8.2-A is not supported.
+@item bf16
+Enable brain half-precision floating-point instructions. This also enables
+Advanced SIMD and floating-point instructions. This option is enabled by
+default for @option{-march=armv8.6-a}. Use of this option with architectures
+prior to Armv8.2-A is not supported.
@end table
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
index 608b89d19ce..5ae39bc6cf0 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
@@ -13,6 +13,92 @@
#error "__ARM_FEATURE_TME is defined but should not be!"
#endif
+/* Test Armv8.6-a features. */
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a")
+
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a")
+#ifndef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+i8mm")
+#ifndef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nosimd")
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nofp")
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is defined but should not be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+bf16")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+bf16+nosimd")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nofp")
+#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is defined but should not be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC pop_options
+
int
foo (int a)
{
next prev parent reply other threads:[~2019-12-05 15:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-26 17:25 Dennis Zhang
2019-11-29 13:02 ` Richard Sandiford
2019-12-05 15:31 ` Dennis Zhang [this message]
2019-12-06 10:22 ` Richard Sandiford
2019-12-12 17:01 ` Dennis Zhang
2019-12-13 10:23 ` Richard Sandiford
2020-10-29 12:19 ` [PATCH][AArch64] ACLE intrinsics: convert from BFloat16 to Float32 Dennis Zhang
2020-10-29 12:28 ` [PATCH][AArch64] ACLE intrinsics: get low/high half from BFloat16 vector Dennis Zhang
2020-10-30 14:07 ` Richard Sandiford
2020-11-03 11:16 ` Dennis Zhang
2020-11-03 14:05 ` Richard Sandiford
2020-11-03 17:00 ` Dennis Zhang
2020-11-05 20:07 ` Christophe Lyon
2020-10-29 17:48 ` [PATCH][AArch64] ACLE intrinsics: convert from BFloat16 to Float32 Richard Sandiford
2020-11-02 17:27 ` Dennis Zhang
2020-11-02 19:05 ` Richard Sandiford
2020-11-03 13:06 ` Dennis Zhang
2020-12-10 14:26 ` [backport gcc-10][AArch64] ACLE bf16 convert Dennis Zhang
2020-12-10 14:34 ` [backport gcc-10][AArch64] ACLE bf16 get Dennis Zhang
2020-12-11 11:58 ` Kyrylo Tkachov
2020-12-11 16:31 ` Dennis Zhang
2020-12-11 11:23 ` [backport gcc-10][AArch64] ACLE bf16 convert Kyrylo Tkachov
2020-12-11 16:35 ` Dennis Zhang
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