From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 52890 invoked by alias); 2 Sep 2019 12:41:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 52881 invoked by uid 89); 2 Sep 2019 12:41:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-5.3 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.1 spammy=malfunction X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 02 Sep 2019 12:41:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81A44337; Mon, 2 Sep 2019 05:41:41 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E9D133F246; Mon, 2 Sep 2019 05:41:40 -0700 (PDT) Subject: Re: [PATCH][AArch64] Implement ACLE intrinsics for FRINT[32,64][Z,X] To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft , James Greenhalgh , Richard Earnshaw References: <1be1bead-8ea4-0ef2-2952-0b991e5d6621@foss.arm.com> From: Kyrill Tkachov Message-ID: <2493a30d-fb4c-a43f-7bfc-09766867f844@foss.arm.com> Date: Mon, 02 Sep 2019 12:41:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <1be1bead-8ea4-0ef2-2952-0b991e5d6621@foss.arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-09/txt/msg00055.txt.bz2 On 9/2/19 1:16 PM, Kyrill Tkachov wrote: > Hi all, > > This patch implements the ACLE intrinsics to access the > FRINT[32,64][Z,X] scalar[1] and vector[2][3] instructions > from Armv8.5-a. These are enabled when the __ARM_FEATURE_FRINT macro is > defined. > > They're added in a fairly standard way through builtins and unspecs at > the RTL level. > The scalar intrinsics Sorry, some malfunction occurred. The scalar intrinsics are available through whereas the Adv SIMD ones are in Thanks, Kyrill > > Bootstrapped and tested on aarch64-none-linux-gnu. > > Ok for trunk? > Thanks, > Kyrill > > [1] > https://developer.arm.com/docs/101028/latest/data-processing-intrinsics > [2] > https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?page=2&search=vrnd32 > [3] > https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?page=2&search=vrnd64 > > 2019-09-02  Kyrylo Tkachov  > >      * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_FRINT32Z, >      UNSPEC_FRINT32X, UNSPEC_FRINT64Z, UNSPEC_FRINT64X. >      (aarch64_): New define_insn. >      * config/aarch64/aarch64.h (TARGET_FRINT): Define. >      * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define >      __ARM_FEATURE_FRINT when appropriate. >      * config/aarch64/aarch64-simd-builtins.def: Add builtins for > frint32z, >      frint32x, frint64z, frint64x. >      * config/aarch64/arm_acle.h (__rint32zf, __rint32z, __rint64zf, >      __rint64z, __rint32xf, __rint32x, __rint64xf, __rint64x): Define. >      * config/aarch64/arm_neon.h (vrnd32z_f32, vrnd32zq_f32, vrnd32z_f64, >      vrnd32zq_f64, vrnd32x_f32, vrnd32xq_f32, vrnd32x_f64, vrnd32xq_f64, >      vrnd64z_f32, vrnd64zq_f32, vrnd64z_f64, vrnd64zq_f64, vrnd64x_f32, >      vrnd64xq_f32, vrnd64x_f64, vrnd64xq_f64): Define. >      * config/aarch64/iterators.md (VSFDF): Define. >      (FRINTNZX): Likewise. >      (frintnzs_op): Likewise. > > 2019-09-02  Kyrylo Tkachov  > >      * gcc.target/aarch64/acle/rintnzx_1.c: New test. >      * gcc.target/aarch64/simd/vrndnzx_1.c: Likewise. >