From: Andrew Burgess <andrew.burgess@embecosm.com>
To: gcc-patches@gcc.gnu.org
Cc: noamca@mellanox.com, Claudiu.Zissulescu@synopsys.com,
Andrew Burgess <andrew.burgess@embecosm.com>
Subject: [PATCH 04/10] gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns
Date: Fri, 04 Mar 2016 13:26:00 -0000 [thread overview]
Message-ID: <25a8417fd0323d78878b64f02283acf181df52bc.1457097757.git.andrew.burgess@embecosm.com> (raw)
In-Reply-To: <cover.1457097757.git.andrew.burgess@embecosm.com>
In-Reply-To: <cover.1457097757.git.andrew.burgess@embecosm.com>
In the load*_update instructions the constraint 'rI' was being used,
which would accept either a register or a signed 12 bit constant. The
problem is that the 32-bit form of ld with update only takes a signed
9-bit immediate. As such, some ld instructions could be generated that
would, when assembled be 64-bit long, however, GCC believed them to be
32-bit long. This error in the length would cause problems during
branch shortening.
The store*_update have the same restrictions on immediate size, however,
the patterns for these instructions already only accept 9-bit
immediates, and so should be safe.
gcc/ChangeLog:
* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
constraint with separate 'r' and 'Cm2' constraints.
(*load_zeroextendqisi_update): Likewise.
(*load_signextendqisi_update): Likewise.
(*loadhi_update): Likewise.
(*load_zeroextendhisi_update): Likewise.
(*load_signextendhisi_update): Likewise.
(*loadsi_update): Likewise.
(*loadsf_update): Likewise.
---
gcc/ChangeLog.NPS400 | 12 +++++++
gcc/config/arc/arc.md | 96 +++++++++++++++++++++++++--------------------------
2 files changed, 60 insertions(+), 48 deletions(-)
diff --git a/gcc/ChangeLog.NPS400 b/gcc/ChangeLog.NPS400
index 716e413..71463df 100644
--- a/gcc/ChangeLog.NPS400
+++ b/gcc/ChangeLog.NPS400
@@ -1,3 +1,15 @@
+2016-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/arc/arc.md (*loadqi_update): Replace use of 'rI'
+ constraint with separate 'r' and 'Cm2' constraints.
+ (*load_zeroextendqisi_update): Likewise.
+ (*load_signextendqisi_update): Likewise.
+ (*loadhi_update): Likewise.
+ (*load_zeroextendhisi_update): Likewise.
+ (*load_signextendhisi_update): Likewise.
+ (*loadsi_update): Likewise.
+ (*loadsf_update): Likewise.
+
2015-09-08 Andrew Burgess <andrew.burgess@embecosm.com>
Joern Rennecke <joern.rennecke@embecosm.com>
Noam Camus <noamca@mellanox.com>
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 4193d26..99e8e30 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1151,40 +1151,40 @@
;; Note: loadqi_update has no 16-bit variant
(define_insn "*loadqi_update"
- [(set (match_operand:QI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:QI 3 "dest_reg_operand" "=r,r,r")
(match_operator:QI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
- (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+ (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ldb.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*load_zeroextendqisi_update"
- [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
(zero_extend:SI (match_operator:QI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
- (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+ (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ldb.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*load_signextendqisi_update"
- [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
(sign_extend:SI (match_operator:QI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
- (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+ (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ldb.x.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*storeqi_update"
[(set (match_operator:QI 4 "any_mem_operand"
@@ -1201,41 +1201,41 @@
;; ??? pattern may have to be re-written
;; Note: no 16-bit variant for this pattern
(define_insn "*loadhi_update"
- [(set (match_operand:HI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:HI 3 "dest_reg_operand" "=r,r,r")
(match_operator:HI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
- (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+ (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ld%_.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*load_zeroextendhisi_update"
- [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
(zero_extend:SI (match_operator:HI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
- (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+ (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ld%_.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
;; Note: no 16-bit variant for this instruction
(define_insn "*load_signextendhisi_update"
- [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
(sign_extend:SI (match_operator:HI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
- (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+ (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ld%_.x.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*storehi_update"
[(set (match_operator:HI 4 "any_mem_operand"
@@ -1251,16 +1251,16 @@
;; No 16-bit variant for this instruction pattern
(define_insn "*loadsi_update"
- [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
(match_operator:SI 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
- (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+ (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ld.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*storesi_update"
[(set (match_operator:SI 4 "any_mem_operand"
@@ -1275,16 +1275,16 @@
(set_attr "length" "4")])
(define_insn "*loadsf_update"
- [(set (match_operand:SF 3 "dest_reg_operand" "=r,r")
+ [(set (match_operand:SF 3 "dest_reg_operand" "=r,r,r")
(match_operator:SF 4 "any_mem_operand"
- [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
- (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+ [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+ (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ld.a%V4 %3,[%0,%S2]"
- [(set_attr "type" "load,load")
- (set_attr "length" "4,8")])
+ [(set_attr "type" "load,load,load")
+ (set_attr "length" "4,4,8")])
(define_insn "*storesf_update"
[(set (match_operator:SF 4 "any_mem_operand"
--
2.6.4
next prev parent reply other threads:[~2016-03-04 13:26 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-04 13:25 [PATCH 00/10] ARC: Add support for NPS400 variant Andrew Burgess
2016-03-04 13:25 ` [PATCH 01/10] gcc: Add support for mellanox nps400 arc variant Andrew Burgess
2016-03-04 13:26 ` [PATCH 09/10] gcc/arc: Add an nps400 specific testcase Andrew Burgess
2016-03-04 13:26 ` Andrew Burgess [this message]
2016-03-04 13:26 ` [PATCH 06/10] gcc/arc: Add support for nps400 cmem xld/xst instructions Andrew Burgess
2016-03-04 13:26 ` [PATCH 05/10] gcc/arc: convert some constraints to define_constraint Andrew Burgess
2016-03-04 13:26 ` [PATCH 03/10] gcc/arc: generate jump tables in code section for nps400 Andrew Burgess
2016-03-04 13:26 ` [PATCH 08/10] gcc/arc: Mask integer 'L' operands to 32-bit Andrew Burgess
2016-03-04 13:26 ` [PATCH 02/10] gcc/arc: Add -munaligned-access option for nps400 Andrew Burgess
2016-03-04 13:26 ` [PATCH 10/10] gcc/arc: Add __NPS400__ define for nps400 targets Andrew Burgess
2016-03-04 13:26 ` [PATCH 07/10] gcc/arc: Add nps400 bitops support Andrew Burgess
2016-04-21 11:39 ` [PATCHv2 3/7] gcc/arc: convert some constraints to define_constraint Andrew Burgess
2016-04-28 17:16 ` Joern Wolfgang Rennecke
2016-04-21 11:39 ` [PATCHv2 2/7] gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns Andrew Burgess
2016-04-28 17:07 ` Joern Wolfgang Rennecke
2016-04-29 11:59 ` Andrew Burgess
2016-04-29 12:09 ` Joern Wolfgang Rennecke
2016-04-21 11:39 ` [PATCHv2 0/7] ARC: Add support for nps400 variant Andrew Burgess
2016-04-28 15:31 ` Joern Wolfgang Rennecke
2016-04-28 16:55 ` Joern Wolfgang Rennecke
2016-04-29 9:04 ` Claudiu Zissulescu
2016-04-29 10:22 ` Andrew Burgess
2016-04-29 22:17 ` Andrew Burgess
2016-05-02 9:02 ` Claudiu Zissulescu
2016-05-03 10:56 ` Andrew Burgess
2016-05-12 11:30 ` Claudiu Zissulescu
2016-06-14 18:46 ` Joern Wolfgang Rennecke
2016-06-14 23:38 ` [PATCH 0/2] Arc fixes and genrecog warning fix Andrew Burgess
2016-06-14 23:38 ` [PATCH 2/2] gcc/genrecog: Don't warn for missing mode on special predicates Andrew Burgess
2016-06-15 18:08 ` Richard Sandiford
2016-06-30 13:38 ` Andrew Burgess
2016-07-04 8:47 ` Richard Sandiford
2016-07-06 19:43 ` Andrew Burgess
2016-07-13 22:19 ` Jeff Law
2016-06-14 23:38 ` [PATCH 1/2] gcc/arc: New peephole2 and little endian arc test fixes Andrew Burgess
2016-11-16 11:44 ` [PATCHv2 0/7] ARC: Add support for nps400 variant Claudiu Zissulescu
2016-04-21 11:40 ` [PATCHv2 7/7] gcc/arc: Add an nps400 specific testcase Andrew Burgess
2016-04-28 19:14 ` Joern Wolfgang Rennecke
2016-04-21 11:40 ` [PATCHv2 5/7] gcc/arc: Add nps400 bitops support Andrew Burgess
2016-04-28 18:50 ` Joern Wolfgang Rennecke
2016-04-21 11:40 ` [PATCHv2 1/7] gcc/arc: Add support for nps400 cpu type Andrew Burgess
2016-04-28 17:07 ` Joern Wolfgang Rennecke
2016-04-21 11:40 ` [PATCHv2 6/7] gcc/arc: Mask integer 'L' operands to 32-bit Andrew Burgess
2016-04-28 19:09 ` Joern Wolfgang Rennecke
2016-04-21 11:40 ` [PATCHv2 4/7] gcc/arc: Add support for nps400 cmem xld/xst instructions Andrew Burgess
2016-04-28 18:23 ` Joern Wolfgang Rennecke
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