diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c index 94e3f42fd33aaf981c0b4bc1296e41f20346705e..734375d58c0664eb8c58a5a53f180bf9ebd74c9f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ int32_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c index 65f28ccbfdea445b3249b7c8ada9922e89b059da..a91943c38a017e2e26583d80f8e8665b54ed015e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ int64_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c index b23c9d97ba653af798f76f9e8e68968b7c75d074..462531cad54e5bfe21e8a5cbd72ef41200a2399b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t @@ -21,18 +21,6 @@ foo (uint32_t value) return uqshl (value, 1); } -/* -**foo1: -** ... -** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|) -** ... -*/ -uint32_t -foo1 () -{ - return uqshl (1, 1); -} - #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c index 6a3d08eea756afeed57be09b8f2f70dbb3275ac6..6fa97a561e317b7e1dfa11d0ef7f0fdd7ec3b5ee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t @@ -21,18 +21,6 @@ foo (uint64_t value) return uqshll (value, 1); } -/* -**foo1: -** ... -** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) -** ... -*/ -uint64_t -foo1 () -{ - return uqshll (1, 1); -} - #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c index 23afcb8da4c407429fd25c5bfb252e5dbe3ed570..ff97bf5c473bf169c9028eaf7b23f0bcb6a980b6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t @@ -24,7 +24,7 @@ foo (uint32_t value) /* **foo1: ** ... -** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint32_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c index 8014371f47fa8d134d240ebca72d9500978cbbe4..ff6a69d300fa64782777f9952d81edf45e115664 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c @@ -12,7 +12,7 @@ extern "C" { /* **foo: ** ... -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t @@ -24,7 +24,7 @@ foo (uint64_t value) /* **foo1: ** ... -** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|) +** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|) ** ... */ uint64_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c index b262bf94d39315a18af4098cfcb2cebc0acf9338..a6a059a19e959c8e3855f0596bdad4d694fcb391 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c index d349caed36ac1ed5d830dbad09c84d301840cfb9..942111339f0debdd42c1962f3892f1a8e07af2de 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c index 5166993a3555858f5cf8c98a78f2641d5eb96533..3b68bb6ac33eabd0d2f825f5c7728740b8935dd5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c index 080bd61d23852bc5786691646223e0500ec31e13..82228491043202273e1254ef3e694cbf2d731735 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c index 45e6ff03623c41e6489596866d00af30a4d2f7e2..0d4cb779254982b760d3ae91227df2b8e700459f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c index 54f141b20931e9efc86224bc90f0af0c38306eec..a0ba6825d8c978fa3814e93c5b160fef59b3ea75 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1 ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c index 06d5bae09da518c35933aa526ad8d8d71ea5445a..47f5f22dde935ca0ef1ae592e6ff40b07affb616 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c index e2111cfd16aeff466376547bc169bf09b61338ae..55a961be2178b5bc2321321e3140b1dcb1c7de50 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c index 66a5c4c9da3e3d1fb1be8db264a3ab45f0cc1c05..dcbaef1a5717cdce8fe6ee7b715f0346c13bbde0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c index 9306f152cdeb0c9daba19b3e3855ddcd3d9f83aa..08f67f665c1c2137ad948b4c077540d4e394cf6d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c @@ -20,9 +20,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c index 0b5040f0b2a23720bdb61f82af06c8a754dbc612..803246c32352d8108b27365b1e7828367629f293 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c index df211a64daad398250e253a1967a03c576dd5ba8..22d2b4355bc12477f9899f5c80b0c42ad473733f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c @@ -16,9 +16,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c index 217cfa7ac2136f4938e4921527b52d539c870b7f..7a332610c69392032289633c2e67f46efe98df9e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c index dad04d05d68c772f3453443748b446b623315651..609021965022f442ad48f9db4a36bd7e42464a7f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c @@ -26,9 +26,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1 ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c index cd033640bcc0487c59c51c4aae1430596773855b..523fa32ee0d8e7c66f208c59d084a91cd663f860 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t @@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ int32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c index 6ca0c753b5e45cbb7a48dc060901635f21644095..ff720fd2df589a49684545a1afc4378a46b98868 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c @@ -22,9 +22,7 @@ extern "C" { ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t @@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry) ** ... ** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|) ** ... -** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|) -** ... -** and (?:ip|fp|r[0-9]+), #1(?: @.*|) +** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|) ** ... */ uint32x4_t diff --git a/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c new file mode 100644 index 0000000000000000000000000000000000000000..1ad91070d93da13583eb37edb2b41135972bf70a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c @@ -0,0 +1,66 @@ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_mve.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo11: +** ... +** movs r0, #2 +** ... +*/ +uint32_t +foo11 () +{ + return uqshl (1, 1); +} + +/* +**foo12: +** ... +** movs r0, #2 +** movs r1, #0 +** ... +*/ +uint64_t +foo12 () +{ + return uqshll (1, 1); +} + +/* +**foo13: +** ... +** movs r0, #1 +** ... +*/ +uint32_t +foo13 () +{ + return uqshr (3, 1); +} + +/* +**foo13: +** ... +** movs r0, #2 +** movs r1, #0 +** ... +*/ +uint64_t +foo13 () +{ + return uqshrl (3, 1); +} + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */