From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.35]) by sourceware.org (Postfix) with UTF8SMTPS id 8E7E13854146 for ; Fri, 5 May 2023 09:41:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8E7E13854146 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683279709; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=TrrmeepKoAYLgs9aTCp0XHVAEMWetrIGO35SV1PkaOU=; b=V+LL3HD0I+RyujOUHb4dC93cT/c5Q8IpoXWrOE1+wbrp/BTI9YL0++sgXKnei4cYXoeFv4 zd/LXj4ur6Qrdptqac0w525bWq8dO0hPYlGzfWP/9MeMApjaa19ab/TC+5aYDiDALOR2uO wWpL/Vd1dtSyGpJj3a1Ghu5lti9LXoOwsRwQ/KnL65LrBKWZ9r294paWexIocIma2GaV3u lm4a3RYk2I6dpKXDxaMBorpKBsUFuN1dX6nt4jvm4LytObRe4pn0cy7xHUxOmYVo90jM8I fn9TngxgVBnap/Q3E5SMHcoXU2sl4tUDbEnosg6972GiJJH3JPlTkVWImqNJ3Q== From: "Jie Mei" Subject: [PATCH 7/8] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 Message-Id: <2672fed4a8b512b5c73661ac76bd08ef4cda24a6.1683273172.git.jie.mei@oss.cipunited.com> X-Lms-Return-Path: To: References: In-Reply-To: Content-Type: multipart/alternative; boundary=209d757fd84cdf8bcfd4c1bed16e068a0ec1d53851140e41c561656f5388 X-Mailer: git-send-email 2.40.1 Content-Transfer-Encoding: 8bit Date: Fri, 05 May 2023 17:41:39 +0800 Mime-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --209d757fd84cdf8bcfd4c1bed16e068a0ec1d53851140e41c561656f5388 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * gcc/config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (ISA_HAS_LL_SC): Same as above. --- gcc/config/mips/mips.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a5c121088b7..1947be25aca 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1247,7 +1247,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) =20 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ -#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >=3D 6) +#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >=3D 6 \ + || ISA_HAS_MIPS16E2) =20 /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. @@ -1340,7 +1341,8 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >=3D 2 && !TARGET_MIPS16) =20 /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >=3D MIPS_ISA_MIPS2 || TARGET_MIPS3900) &&= !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >=3D MIPS_ISA_MIPS2 || TARGET_MIPS3900) \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1349,7 +1351,8 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >=3D MIPS_ISA_MIPS2 && !TARGET_MIPS5900 &&= !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >=3D MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ --=20 2.40.1= --209d757fd84cdf8bcfd4c1bed16e068a0ec1d53851140e41c561656f5388--