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From: Lulu Cheng <chenglulu@loongson.cn>
To: Xi Ruoyao <xry111@xry111.site>, gcc-patches@gcc.gnu.org
Cc: Wang Xuerui <i@xen0n.name>, Chenghua Xu <xuchenghua@loongson.cn>
Subject: Re: [PATCH] LoongArch: Add prefetch instruction
Date: Wed, 28 Sep 2022 16:31:58 +0800	[thread overview]
Message-ID: <274b4e27-6f4f-3d97-84ad-b5aae19e1002@loongson.cn> (raw)
In-Reply-To: <20220925112537.2209847-1-xry111@xry111.site>

Hi,

My colleague is testing the performance data of prefetch and prefetchx.

And will submit both supports together if there is no problem.


在 2022/9/25 下午7:25, Xi Ruoyao 写道:
> The test pr106397.c fails on LoongArch because we don't have defined
> prefetch instruction.  We can silence the test for LoongArch, but it's
> not too difficult to add the prefetch instruction so add it now.
>
> -- >8 --
>
> gcc/ChangeLog:
>
> 	* config/loongarch/constraints.md (ZD): New address constraint.
> 	* config/loongarch/loongarch.md (prefetch): New insn.
> ---
>   gcc/config/loongarch/constraints.md |  6 ++++++
>   gcc/config/loongarch/loongarch.md   | 14 ++++++++++++++
>   2 files changed, 20 insertions(+)
>
> diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md
> index 43cb7b5f0f5..93da5970958 100644
> --- a/gcc/config/loongarch/constraints.md
> +++ b/gcc/config/loongarch/constraints.md
> @@ -190,3 +190,9 @@ (define_memory_constraint "ZB"
>     The offset is zero"
>     (and (match_code "mem")
>          (match_test "REG_P (XEXP (op, 0))")))
> +
> +(define_address_constraint "ZD"
> +  "An address operand whose address is formed by a base register and offset
> +   that is suitable for use in instructions with the same addressing mode
> +   as @code{preld}."
> +   (match_test "loongarch_12bit_offset_address_p (op, mode)"))
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index 214b14bddd3..84c1bd1c0d6 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -2137,6 +2137,20 @@ (define_insn "loongarch_dbar"
>     ""
>     "dbar\t%0")
>   
> +(define_insn "prefetch"
> +  [(prefetch (match_operand 0 "address_operand" "ZD")
> +	     (match_operand 1 "const_uimm5_operand" "i")
> +	     (match_operand 2 "const_int_operand" "n"))]
> +  ""
> +{
> +  switch (INTVAL (operands[1]))
> +  {
> +    case 0: return "preld\t0,%a0";
> +    case 1: return "preld\t8,%a0";
> +    default: gcc_unreachable ();
> +  }
> +})
> +
>   \f
>   
>   ;; Privileged state instruction


  reply	other threads:[~2022-09-28  8:32 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-25 11:25 Xi Ruoyao
2022-09-28  8:31 ` Lulu Cheng [this message]
2022-09-28  8:41   ` Xi Ruoyao

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