From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 7EB84385828D for ; Wed, 28 Sep 2022 08:32:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7EB84385828D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from [10.20.4.52] (unknown [10.20.4.52]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxT+B+BjRj9TIjAA--.1703S2; Wed, 28 Sep 2022 16:31:59 +0800 (CST) Subject: Re: [PATCH] LoongArch: Add prefetch instruction To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: Wang Xuerui , Chenghua Xu References: <20220925112537.2209847-1-xry111@xry111.site> From: Lulu Cheng Message-ID: <274b4e27-6f4f-3d97-84ad-b5aae19e1002@loongson.cn> Date: Wed, 28 Sep 2022 16:31:58 +0800 User-Agent: Mozilla/5.0 (X11; Linux mips64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20220925112537.2209847-1-xry111@xry111.site> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8CxT+B+BjRj9TIjAA--.1703S2 X-Coremail-Antispam: 1UD129KBjvJXoW7WF15XF47GryfJFWfCF4UJwb_yoW8ury3pr Z3A3ZIyF48JFsIg39Fy345Xws8JryxKw12vay3t34fCw45Wr1UZ3W0kr9ruF98Ww4rtr1S qF1Fga1jqa1Ut37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUva14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvEwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7I2V7IY0VAS07AlzVAY IcxG8wCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2 IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v2 6r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2 IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv 67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyT uYvjfUozVbDUUUU X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, My colleague is testing the performance data of prefetch and prefetchx. And will submit both supports together if there is no problem. ÔÚ 2022/9/25 ÏÂÎç7:25, Xi Ruoyao дµÀ: > The test pr106397.c fails on LoongArch because we don't have defined > prefetch instruction. We can silence the test for LoongArch, but it's > not too difficult to add the prefetch instruction so add it now. > > -- >8 -- > > gcc/ChangeLog: > > * config/loongarch/constraints.md (ZD): New address constraint. > * config/loongarch/loongarch.md (prefetch): New insn. > --- > gcc/config/loongarch/constraints.md | 6 ++++++ > gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md > index 43cb7b5f0f5..93da5970958 100644 > --- a/gcc/config/loongarch/constraints.md > +++ b/gcc/config/loongarch/constraints.md > @@ -190,3 +190,9 @@ (define_memory_constraint "ZB" > The offset is zero" > (and (match_code "mem") > (match_test "REG_P (XEXP (op, 0))"))) > + > +(define_address_constraint "ZD" > + "An address operand whose address is formed by a base register and offset > + that is suitable for use in instructions with the same addressing mode > + as @code{preld}." > + (match_test "loongarch_12bit_offset_address_p (op, mode)")) > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index 214b14bddd3..84c1bd1c0d6 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -2137,6 +2137,20 @@ (define_insn "loongarch_dbar" > "" > "dbar\t%0") > > +(define_insn "prefetch" > + [(prefetch (match_operand 0 "address_operand" "ZD") > + (match_operand 1 "const_uimm5_operand" "i") > + (match_operand 2 "const_int_operand" "n"))] > + "" > +{ > + switch (INTVAL (operands[1])) > + { > + case 0: return "preld\t0,%a0"; > + case 1: return "preld\t8,%a0"; > + default: gcc_unreachable (); > + } > +}) > + > > > ;; Privileged state instruction