From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id 543A33852200 for ; Mon, 21 Nov 2022 15:30:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 543A33852200 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=ispras.ru Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ispras.ru Received: from [10.10.3.121] (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTPS id CDC61400CBDC; Mon, 21 Nov 2022 15:30:01 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru CDC61400CBDC Date: Mon, 21 Nov 2022 18:30:01 +0300 (MSK) From: Alexander Monakov To: "Joshi, Tejas Sanjay" cc: "gcc-patches@gcc.gnu.org" , "honza.hubicka@gmail.com" , "Kumar, Venkataramanan" Subject: RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers In-Reply-To: Message-ID: <27b06e9f-1e80-585d-624e-6f50475a5aa8@ispras.ru> References: <8e489785-b181-fbcf-e029-cd75796a6f28@ispras.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 21 Nov 2022, Joshi, Tejas Sanjay wrote: > I have addressed all your comments in the patch attached here. I have also > used znver4-direct for avx512 insns. Thanks. > * This patch increased the insn-automata.cc size from 201502 to 214902. Assuming it's the number of lines of code, I have 102847, perhaps you're measuring without my patches? You can use 'size -A gcc/insn-automata.o' to measure binary size growth. > * Compile time and binary size on my machine remains same. > * Make check and bootstrap build have no issues. > * Spec cpu2017 also don't have any issues with this patch. > > Is this ok for trunk? I cannot approve or reject your patch, this is up to Honza who I believe was investigating if combining this with older Zen models makes sense. In the meantime, I see a few more issues that can be easily corrected, please see below. > --- /dev/null > +++ b/gcc/config/i386/znver4.md > +;; FSQRT > +(define_insn_reservation "znver4_fsqrt" 22 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "fpspc") > + (and (eq_attr "mode" "XF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fdiv*20") This should be znver4-fdiv*10 (not *20) according to Agner Fog's measurements. > +;; FDIV > +(define_insn_reservation "znver4_fp_div" 15 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "fdiv") > + (eq_attr "memory" "none"))) > + "znver4-direct,znver4-fdiv*15") znver4-fdiv*6 instead of *15 here and in two patterns following this one. > +(define_insn_reservation "znver4_sse_div_pd" 13 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V4DF,V2DF,V1DF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fdiv*7") Agner Fog's measurements indicate fdiv*5 here. > + > +(define_insn_reservation "znver4_sse_div_ps" 10 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fdiv*5") Agner Fog's measurements indicate fdiv*3 here. > + > +(define_insn_reservation "znver4_sse_div_pd_load" 20 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V4DF,V2DF,V1DF") > + (eq_attr "memory" "load")))) > + "znver4-direct,znver4-load,znver4-fdiv*7") fdiv*5? > + > +(define_insn_reservation "znver4_sse_div_ps_load" 17 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V8SF,V4SF,V2SF,SF") > + (eq_attr "memory" "load")))) > + "znver4-direct,znver4-load,znver4-fdiv*5") fdiv*3? > +(define_insn_reservation "znver4_sse_div_pd_evex" 13 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V8DF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fdiv*7") This should be twice as much as the corresponding SSE/AVX instruction (fdiv*14 or fdiv*10; Agner Fog measured 9 cycles as reciprocal throughput). > + > +(define_insn_reservation "znver4_sse_div_ps_evex" 10 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V16SF") > + (eq_attr "memory" "none")))) > + "znver4-direct,znver4-fdiv*5") Likewise (fdiv*6). > +(define_insn_reservation "znver4_sse_div_pd_evex_load" 20 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V8DF") > + (eq_attr "memory" "load")))) > + "znver4-direct,znver4-load,znver4-fdiv*7") Likewise. > +(define_insn_reservation "znver4_sse_div_ps_evex_load" 17 > + (and (eq_attr "cpu" "znver4") > + (and (eq_attr "type" "ssediv") > + (and (eq_attr "mode" "V16SF") > + (eq_attr "memory" "load")))) > + "znver4-direct,znver4-load,znver4-fdiv*5") Likewise. Alexander