* [patch,avr,applied] Tweak xor insn constraints
@ 2024-03-18 7:49 Georg-Johann Lay
0 siblings, 0 replies; only message in thread
From: Georg-Johann Lay @ 2024-03-18 7:49 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 893 bytes --]
xor insn allows some more values without the requirement
of a scratch register. This patch adds new constraint
alternative for such values. The output function avr_out_bitop
already handles these cases, so no change is needed there.
Johann
--
avr.md - Tweak xor insn constraints.
xor insn can handle some more values without the requirement of a
scratch register. This patch adds a new constraint alternative for
such values. The output function avr_out_bitop already handles
these cases, so no change is needed there.
gcc/
* config/avr/constraints.md (CX2, CX3, CX4): New constraints.
* config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
* config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
* config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
(xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
(xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
[-- Attachment #2: x.diff --]
[-- Type: text/x-patch, Size: 8400 bytes --]
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index bb680312117..dc23cfbf461 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -101,6 +101,7 @@ extern const char* avr_out_xload (rtx_insn *, rtx*, int*);
extern const char* avr_out_cpymem (rtx_insn *, rtx*, int*);
extern const char* avr_out_insert_bits (rtx*, int*);
extern bool avr_popcount_each_byte (rtx, int, int);
+extern bool avr_xor_noclobber_dconst (rtx, int);
extern bool avr_has_nibble_0xf (rtx);
extern int extra_constraint_Q (rtx x);
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 00fce8da15f..12c59668b4c 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -281,6 +281,31 @@ avr_popcount_each_byte (rtx xval, int n_bytes, int pop_mask)
}
+/* Constraint helper function. XVAL is a CONST_INT. Return true if we
+ can perform XOR without a clobber reg, provided the operation is on
+ a d-register. This means each byte is in { 0, 0xff, 0x80 }. */
+
+bool
+avr_xor_noclobber_dconst (rtx xval, int n_bytes)
+{
+ machine_mode mode = GET_MODE (xval);
+
+ if (VOIDmode == mode)
+ mode = SImode;
+
+ for (int i = 0; i < n_bytes; ++i)
+ {
+ rtx xval8 = simplify_gen_subreg (QImode, xval, mode, i);
+ unsigned int val8 = UINTVAL (xval8) & GET_MODE_MASK (QImode);
+
+ if (val8 != 0 && val8 != 0xff && val8 != 0x80)
+ return false;
+ }
+
+ return true;
+}
+
+
/* Access some RTX as INT_MODE. If X is a CONST_FIXED we can get
the bit representation of X by "casting" it to CONST_INT. */
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index bc408633eb5..97f42be7729 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -4741,10 +4741,10 @@ (define_insn "*xorqi3"
[(set_attr "length" "1")])
(define_insn_and_split "xorhi3"
- [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
- (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
- (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,Cx2,CX2,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))]
""
"#"
"&& reload_completed"
@@ -4755,10 +4755,10 @@ (define_insn_and_split "xorhi3"
(clobber (reg:CC REG_CC))])])
(define_insn "*xorhi3"
- [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
- (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
- (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ [(set (match_operand:HI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,Cx2,CX2,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))
(clobber (reg:CC REG_CC))]
"reload_completed"
{
@@ -4767,14 +4767,14 @@ (define_insn "*xorhi3"
return avr_out_bitop (insn, operands, NULL);
}
- [(set_attr "length" "2,2,4")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")])
+ [(set_attr "length" "2,2,4,4")
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
(define_insn_and_split "xorpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
- (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
- (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))]
+ [(set (match_operand:PSI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,CX3,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))]
""
"#"
"&& reload_completed"
@@ -4785,10 +4785,10 @@ (define_insn_and_split "xorpsi3"
(clobber (reg:CC REG_CC))])])
(define_insn "*xorpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
- (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
- (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ [(set (match_operand:PSI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,CX3,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))
(clobber (reg:CC REG_CC))]
"reload_completed"
{
@@ -4799,14 +4799,14 @@ (define_insn "*xorpsi3"
return avr_out_bitop (insn, operands, NULL);
}
- [(set_attr "length" "3,6,6")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")])
+ [(set_attr "length" "3,6,6,6")
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
(define_insn_and_split "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
- (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cx4,CX4,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))]
""
"#"
"&& reload_completed"
@@ -4817,10 +4817,10 @@ (define_insn_and_split "xorsi3"
(clobber (reg:CC REG_CC))])])
(define_insn "*xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
- (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
- (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ [(set (match_operand:SI 0 "register_operand" "=??r,r ,d ,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0 ,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cx4,CX4,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X ,&d"))
(clobber (reg:CC REG_CC))]
"reload_completed"
{
@@ -4832,8 +4832,8 @@ (define_insn "*xorsi3"
return avr_out_bitop (insn, operands, NULL);
}
- [(set_attr "length" "4,8,8")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")])
+ [(set_attr "length" "4,8,8,8")
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
(define_split
diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md
index fac54da17db..b4e5525d197 100644
--- a/gcc/config/avr/constraints.md
+++ b/gcc/config/avr/constraints.md
@@ -169,7 +169,7 @@ (define_constraint "Ca4"
(match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<7) | (1<<8))")))
(define_constraint "Co1"
- "Constant 1-byte integer that allows AND by means of SET + BLD."
+ "Constant 1-byte integer that allows OR by means of SET + BLD."
(and (match_code "const_int")
(match_test "avr_popcount_each_byte (op, 1, 1<<1)")))
@@ -218,6 +218,21 @@ (define_constraint "Cx4"
(and (match_code "const_int")
(match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<8))")))
+(define_constraint "CX2"
+ "Constant 2-byte integer that allows XOR without clobber register but requires a d-register."
+ (and (match_code "const_int")
+ (match_test "avr_xor_noclobber_dconst (op, 2)")))
+
+(define_constraint "CX3"
+ "Constant 3-byte integer that allows XOR without clobber register but requires a d-register."
+ (and (match_code "const_int")
+ (match_test "avr_xor_noclobber_dconst (op, 3)")))
+
+(define_constraint "CX4"
+ "Constant 4-byte integer that allows XOR without clobber register but requires a d-register."
+ (and (match_code "const_int")
+ (match_test "avr_xor_noclobber_dconst (op, 4)")))
+
(define_constraint "Csp"
"Integer constant in the range -11 @dots{} 6."
(and (match_code "const_int")
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2024-03-18 7:49 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-18 7:49 [patch,avr,applied] Tweak xor insn constraints Georg-Johann Lay
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).