From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Jeff Law <jlaw@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Kito Cheng <kito.cheng@gmail.com>,
Vineet Gupta <vineetg@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>
Subject: Re: [PATCH] RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb
Date: Sat, 12 Nov 2022 17:24:06 -0700 [thread overview]
Message-ID: <2b5a37c6-e7bc-6f65-eb40-326dba810253@gmail.com> (raw)
In-Reply-To: <20221108195456.2701279-1-philipp.tomsich@vrull.eu>
On 11/8/22 12:54, Philipp Tomsich wrote:
> If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
> not a5,a0
> srai a5,a5,63
> and a0,a1,a5
> missing the opportunity to combine the NOT and AND into an ANDN.
>
> This adds a define_split to help the combiner reassociate the NOT with
> the AND.
>
>
> gcc/ChangeLog:
>
> * config/riscv/bitmanip.md: New define_split.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zbb-srai-andn.c: New test.
OK.
FWIW, combine can be pretty sneaky in manipulating the result of a scc
style insn. I've seen a port with pages and pages of special patterns
to match what simplify_if_then_else would do.
Jeff
next prev parent reply other threads:[~2022-11-13 0:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 19:54 Philipp Tomsich
2022-11-13 0:24 ` Jeff Law [this message]
2022-11-13 15:48 ` Philipp Tomsich
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