Re: [PATCH] LoongArch: Remove redundant barrier instructions before LL-SC loops

[Xi Ruoyao <xry111@xry111.site>]

On Wed, 2023-11-08 at 16:27 +0800, Xi Ruoyao wrote:
> On Wed, 2023-11-08 at 09:49 +0800, chenglulu wrote:
> > 
> > 在 2023/11/6 下午7:36, Xi Ruoyao 写道:
> > > This is isomorphic to the LLVM changes [1-2].
> > > 
> > > On LoongArch, the LL and SC instructions has memory barrier semantics:
> > > 
> > > - LL: <memory-barrier> + <load-exclusive>
> > > - SC: <store-conditional> + <memory-barrier>
> > > 
> > > But the compare and swap operation is allowed to fail, and if it fails
> > > the SC instruction is not executed, thus the guarantee of acquiring
> > > semantics cannot be ensured. Therefore, an acquire barrier needs to be
> > > generated when failure_memorder includes an acquire operation.
> > > 
> > > On CPUs implementing LoongArch v1.10 or later, "dbar 0b10100" is an
> > > acquire barrier; on CPUs implementing LoongArch v1.00, it is a full
> > > barrier.  So it's always enough for acquire semantics.  OTOH if an
> > > acquire semantic is not needed, we still needs the "dbar 0x700" as the
> > > load-load barrier like all LL-SC loops.
> > 
> > I don't think there's a problem with the logic. I'm also working on 
> > correcting the content of the atomic functions now, and I'm doing a 
> > correctness test, including this modification, and I'll email you back
> > after the correctness test is completed.
> 
> Ok.  I'd like to note that we now have only 10 days before GCC 14 stage
> 1 ends, so we'd be better hurry.

Update: I've bootstrapped and regtested it on a LA664 and there is no
regression.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University