From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>,
richard.sandiford@arm.com
Subject: Re: [PATCH][AArch64]: Use UNSPEC_LD1_SVE for all LD1 loads
Date: Tue, 18 May 2021 11:38:45 +0100 [thread overview]
Message-ID: <2d6603b3-1d35-075f-cfff-17cd3f0bab01@arm.com> (raw)
In-Reply-To: <mptmtsxxmdw.fsf@arm.com>
[-- Attachment #1: Type: text/plain, Size: 2313 bytes --]
Hi,
Using aarch64_pred_mov for these was tricky as it did both store and
load. Furthermore there was some concern it might allow for a predicated
mov to end up as a mem -> mem and a predicated load being wrongfully
reloaded to a full-load to register. So instead we decided to let the
extending aarch64_load_* patterns accept both UNSPEC_LD1_SVE and
UNSPEC_PRED_X.
Is this OK for trunk?
Kind regards,
Andre Vieira
gcc/ChangeLog:
2021-05-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/aarch64/iterators.md (SVE_PRED_LOAD): New iterator.
(pred_load): New int attribute.
* config/aarch64/aarch64-sve.md
(aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
Use SVE_PRED_LOAD
enum iterator and corresponding pred_load attribute.
* config/aarch64/aarch64-sve-builtins-base.cc (expand): Update
call to code_for_aarch64_load.
gcc/testsuite/ChangeLog:
2021-05-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/aarch64/sve/logical_unpacked_and_2.c: Change
scan-assembly-times to scan-assembly not for superfluous uxtb.
* gcc.target/aarch64/sve/logical_unpacked_and_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_and_7.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_2.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_eor_7.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_2.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_3.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_4.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_6.c: Likewise.
* gcc.target/aarch64/sve/logical_unpacked_orr_7.c: Likewise.
* gcc.target/aarch64/sve/ld1_extend.c: New test.
[-- Attachment #2: ld1_2.patch --]
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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index dfdf0e2fd186389cbddcff51ef52f8778d7fdb24..8fd6d3fb3171f56b4ceacaf7ea812bc696117210 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1123,7 +1123,7 @@ public:
rtx
expand (function_expander &e) const OVERRIDE
{
- insn_code icode = code_for_aarch64_load (extend_rtx_code (),
+ insn_code icode = code_for_aarch64_load (UNSPEC_LD1_SVE, extend_rtx_code (),
e.vector_mode (0),
e.memory_vector_mode ());
return e.use_contiguous_load_insn (icode);
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 7db2938bb84e04d066a7b07574e5cf344a3a8fb6..a5663200d51b95684b4dc0caefd527a525aebd52 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1287,7 +1287,7 @@ (define_insn "vec_mask_load_lanes<mode><vsingle>"
;; -------------------------------------------------------------------------
;; Predicated load and extend, with 8 elements per 128-bit block.
-(define_insn_and_rewrite "@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
+(define_insn_and_rewrite "@aarch64_load<SVE_PRED_LOAD:pred_load>_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
[(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
(unspec:SVE_HSDI
[(match_operand:<SVE_HSDI:VPRED> 3 "general_operand" "UplDnm")
@@ -1295,7 +1295,7 @@ (define_insn_and_rewrite "@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PA
(unspec:SVE_PARTIAL_I
[(match_operand:<SVE_PARTIAL_I:VPRED> 2 "register_operand" "Upl")
(match_operand:SVE_PARTIAL_I 1 "memory_operand" "m")]
- UNSPEC_LD1_SVE))]
+ SVE_PRED_LOAD))]
UNSPEC_PRED_X))]
"TARGET_SVE && (~<SVE_HSDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
"ld1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_HSDI:Vctype>, %2/z, %1"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index fb6e228651eae6a2db8c1ac755885ae7ad9225d6..8c17929cea4c83cc9f80b4cde950407ba4eb0416 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2509,6 +2509,10 @@ (define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE
(define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
+(define_int_iterator SVE_PRED_LOAD [UNSPEC_PRED_X UNSPEC_LD1_SVE])
+
+(define_int_attr pred_load [(UNSPEC_PRED_X "_x") (UNSPEC_LD1_SVE "")])
+
(define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE])
(define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c b/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f78cb4b3e4445c4da93b00ae78d6ef6fec1b2de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 --param vect-partial-vector-usage=1" } */
+
+void foo (signed char * __restrict__ a, signed char * __restrict__ b, short * __restrict__ c, int n)
+{
+ for (int i = 0; i < n; ++i)
+ c[i] = a[i] + b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tld1sb\t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
index 08b274512e1c6ce8f5845084a664b2fa0456dafe..505767afaca0e5e9607442b5a73c0b1bc185993a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
index c823470ca925ee66929475f74fa8d94bc4735594..f7d43607432188fd46e69186013eab868faf9605 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
index 52c92911d9b548662d43b23816e4d450a9e67846..1aef9033e6ceab13216722df57cf40616077bb71 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
index 1552ed85302373bb16ad8265f5c84cea71ccbc66..fb58b52ee03528a04a7f8fb4b1f78cf1e583d80c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
index 484d9daf38f0779109484eab5a2a03a626c16fe8..34b2cc05734a1cbcf043d8068345f57a7c480090 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
index 23ddeb9f9b11f80783e1b173696a15d1d73762a3..529c07362daa19182abbf87619f806199b1e305a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
index 4dd1e085646c6d0e6d3d4e02534c94ea592ea7be..b6b0119a7e725ab69804d27558caa1c1979a26ea 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
index a31a2d425faa11c6faa5306d4c0a7e5a5fa086d8..a61eed441de3bc44f45729893a28f54dbbbe7914 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
index 416567b21f703d6e0ff3792d2089b923ecde0441..a3fde4bcb183c9d5004fec1e3525a57ad112b7f6 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
index 3f7c3ddbba8a986e01fbdbe51b307bdc3990da37..8e01f3f9ef0bbe4e542ec0b13b01e03387f74221 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
index 593de65a02cd2a16acb48a6dd05163a4e66b7b27..763c81b69c440b75d6a2e821027bad08a9d0558a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
index ec34e753eabf0709696cc4724a0bde2b825c6231..17fddcd3eeecd0b916cc0d8b7de952fd325a2e76 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
index 561a104a23f00759af457e03e8e175589282aeb5..4e8c4d0f9a370e53e9f0ac4c0ed8214f7a47cc71 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
index 3ce1c3fb1e636c7f8ebcf2a7fbaafe20f3b7cfa0..26103cf933b2ba788f21f1ad964cca57958285b2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
index e6a429167ea38dbbbc7e653cd6d47ffbe0bc768d..06e1b586e6eeb2b6634dc422b74047f836545b6c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
/* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */
next prev parent reply other threads:[~2021-05-18 10:38 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 16:26 Andre Vieira (lists)
2021-05-14 17:20 ` Richard Sandiford
2021-05-18 10:38 ` Andre Vieira (lists) [this message]
2021-05-18 11:04 ` Richard Sandiford
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