* [PATCH] RISC-V: Update test expectancies with recent scheduler change
@ 2024-02-23 23:10 Edwin Lu
2024-02-26 13:29 ` Robin Dapp
0 siblings, 1 reply; 10+ messages in thread
From: Edwin Lu @ 2024-02-23 23:10 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, pan2.li, rdapp.gcc, Edwin Lu
Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Bound testcase
assembly matching
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
* gcc.target/riscv/rvv/base/vcreate.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
.../costmodel/riscv/rvv/dynamic-lmul4-6.c | 3 +-
.../costmodel/riscv/rvv/dynamic-lmul4-8.c | 3 +-
.../gcc.target/riscv/rvv/base/pr108185-1.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-2.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-3.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-4.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-5.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-6.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/pr108185-7.c | 25 +++++++++++++----
.../gcc.target/riscv/rvv/base/vcreate.c | 13 +++++++--
.../riscv/rvv/vsetvl/vlmax_back_prop-30.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_back_prop-31.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_single_block-17.c | 28 ++++++++++++++-----
.../riscv/rvv/vsetvl/vlmax_single_block-18.c | 14 ++++++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 9 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 3 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 3 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 8 ++++--
.../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 8 ++++--
23 files changed, 238 insertions(+), 77 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index d2766f5984c..1cb0888f9d8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -20,7 +20,8 @@ foo (uint8_t *restrict a, uint8_t *restrict b, int n)
}
/* { dg-final { scan-assembler {e8,m4} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} >= 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} <= 3 } } */
/* Since we don't support VLA SLP for LMUL = 8, dynamic LMUL cost model start from LMUL = 4. */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-not "Maximum lmul = 8" "vect" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 362c49f1411..0d644fc69bf 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -29,7 +29,8 @@ foo (uint8_t *restrict a, uint8_t *restrict b, int n)
}
/* { dg-final { scan-assembler {e8,m4} } } */
-/* { dg-final { scan-assembler-times {csrr} 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} >= 1 } } */
+/* { dg-final { scan-assembler-bound {csrr} <= 3 } } */
/* Since we don't support VLA SLP for LMUL = 8, dynamic LMUL cost model start from LMUL = 4. */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-not "Maximum lmul = 8" "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index 4c6e88e7eed..898417fd710 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -60,11 +60,24 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index 0844e3e8713..34be4dd5ea1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -60,11 +60,24 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 49a574485fe..89920a1eb47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -60,11 +60,24 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index cef0a11b2d4..31494adab03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -60,11 +60,24 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 3f0d67726bc..e5cd7ebe94c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -60,11 +60,24 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 4ed658899f4..1e4f1cd6564 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -60,11 +60,24 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
index 95b7ff97666..32cee1e2043 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
@@ -60,11 +60,24 @@ test_vbool64_then_vbool32(int8_t * restrict in, int8_t * restrict out) {
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 6 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} <= 2 } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} >= 1 } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} <= 2 } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
index 0fc8c3450f0..aa752440fcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c
@@ -254,6 +254,13 @@ test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2,
return __riscv_vcreate_v_i64m2x4 (v0, v1, v2, v3);
}
-/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 24 } } */
-/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 12 } } */
-/* { dg-final { scan-assembler-times {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} 16 } } */
+// Ideally with O3, should find 0 instances of any vmvnr.v PR113913
+/* { dg-final { scan-assembler-bound {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} >= 24 } } */
+/* { dg-final { scan-assembler-bound {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} <= 36 } } */
+
+/* { dg-final { scan-assembler-bound {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} >= 12 } } */
+/* { dg-final { scan-assembler-bound {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} <= 28 } } */
+
+/* { dg-final { scan-assembler-bound {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} >= 16 } } */
+/* { dg-final { scan-assembler-bound {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} <= 19 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
index 9b0d88ddf97..40ff03400ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -32,7 +32,9 @@ void f (void * restrict in, void * restrict out, void * restrict in2, void * res
}
}
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
@@ -41,4 +43,6 @@ void f (void * restrict in, void * restrict out, void * restrict in2, void * res
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
index ee321fc1fa0..8790806bd3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -33,6 +33,7 @@ void f (void * restrict in, void * restrict out, void * restrict in2, void * res
}
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
@@ -40,7 +41,10 @@ void f (void * restrict in, void * restrict out, void * restrict in2, void * res
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 10 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 006df7edf8d..d47071dd308 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -23,12 +23,26 @@ void foo7 (void * restrict in, void * restrict out)
*(vbool64_t*)(out + 7) = v7;
}
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
/* { dg-final { scan-assembler-times {vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
/* { dg-final { scan-assembler-times {vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index cc6d8221516..26a8b470776 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -29,6 +29,14 @@ void f (void * restrict in, void * restrict out)
}
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
+
+/* { dg-final { scan-assembler-bound {vsetvli} >= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 6 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-Og -g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 476735dcb2e..00a64449ff6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -43,6 +43,11 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 15 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} <= 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index c7b7db33849..86969c9cc40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -54,4 +54,5 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int con
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 13 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 80ff75f6d2a..3575c691a0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -53,5 +53,6 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond1, int con
*(vint16mf4_t*)(out + 30000) = v;
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 9 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 15 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 127dc7ff06d..0391286e2b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -18,5 +18,9 @@ void f (void * restrict in, void * restrict out, int n)
}
}
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 127dc7ff06d..0391286e2b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -18,5 +18,9 @@ void f (void * restrict in, void * restrict out, int n)
}
}
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} >= 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} <= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts "-g" no-opts "-funroll-loops" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index e19e869e241..a4d98ae3111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -31,5 +31,9 @@ void foo (void * restrict in, void * restrict out, int n)
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 13 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 90eca5b1ae6..39fffc3597c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -41,5 +41,9 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n)
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 13 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 17b217bc82c..5ec1b14bc52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -42,6 +42,10 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
*(vint32mf2_t*)(out + i + 700) = v6;
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 13 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 17b217bc82c..5ec1b14bc52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -42,6 +42,10 @@ void foo (int8_t * restrict in, int8_t * restrict out, int n, int cond)
*(vint32mf2_t*)(out + i + 700) = v6;
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} >= 7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli} <= 13 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} >= 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-bound {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} <= 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
+
/* { dg-final { scan-assembler-not {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
--
2.34.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-23 23:10 [PATCH] RISC-V: Update test expectancies with recent scheduler change Edwin Lu
@ 2024-02-26 13:29 ` Robin Dapp
2024-02-27 1:21 ` juzhe.zhong
0 siblings, 1 reply; 10+ messages in thread
From: Robin Dapp @ 2024-02-26 13:29 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain, pan2.li, juzhe.zhong
On 2/24/24 00:10, Edwin Lu wrote:
> Given the recent change with adding the scheduler pipeline descriptions,
> many scan-dump failures emerged. Relax the expected assembler output
> conditions on the affected tests to reduce noise.
I'm not entirely sure yet about relaxing the scans like this.
There seem to be uarchs that want to minimize vsetvls under all
circumstances while others don't seem to care all that much. We could
(not must) assume that the tests that now regress have been written
with this minimization aspect in mind and that we'd want to be sure
that we still manage to emit the minimal number of vsetvls.
Why is the new upper bound acceptable? What if a vector_load cost
of 12 (or so) causes even more vsetvls? The 6 in generic_ooo is more
or less arbitrary chosen.
My suggestion before was to create another sched model that has
load costs like before and run the regressing tests with that
model. That's of course also not really ideal and actually
shoehorned a bit, in particular as no scheduling also increases
the number of vsetvls.
Juzhe: What's your intention with those tests? I'd suppose you
want the vsetvl number to be minimal here and not higher? Did you
plan to add a particular scheduling model or are you happy with
the default (all 1) latencies?
Regards
Robin
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-26 13:29 ` Robin Dapp
@ 2024-02-27 1:21 ` juzhe.zhong
2024-02-27 15:22 ` Jeff Law
0 siblings, 1 reply; 10+ messages in thread
From: juzhe.zhong @ 2024-02-27 1:21 UTC (permalink / raw)
To: Robin Dapp, Edwin Lu, gcc-patches; +Cc: Robin Dapp, gnu-toolchain, pan2.li
[-- Attachment #1: Type: text/plain, Size: 1684 bytes --]
If the scheduling model increases the vsetvls, we shouldn't set it as default scheduling model
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2024-02-26 21:29
To: Edwin Lu; gcc-patches
CC: rdapp.gcc; gnu-toolchain; pan2.li; juzhe.zhong@rivai.ai
Subject: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
On 2/24/24 00:10, Edwin Lu wrote:
> Given the recent change with adding the scheduler pipeline descriptions,
> many scan-dump failures emerged. Relax the expected assembler output
> conditions on the affected tests to reduce noise.
I'm not entirely sure yet about relaxing the scans like this.
There seem to be uarchs that want to minimize vsetvls under all
circumstances while others don't seem to care all that much. We could
(not must) assume that the tests that now regress have been written
with this minimization aspect in mind and that we'd want to be sure
that we still manage to emit the minimal number of vsetvls.
Why is the new upper bound acceptable? What if a vector_load cost
of 12 (or so) causes even more vsetvls? The 6 in generic_ooo is more
or less arbitrary chosen.
My suggestion before was to create another sched model that has
load costs like before and run the regressing tests with that
model. That's of course also not really ideal and actually
shoehorned a bit, in particular as no scheduling also increases
the number of vsetvls.
Juzhe: What's your intention with those tests? I'd suppose you
want the vsetvl number to be minimal here and not higher? Did you
plan to add a particular scheduling model or are you happy with
the default (all 1) latencies?
Regards
Robin
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-27 1:21 ` juzhe.zhong
@ 2024-02-27 15:22 ` Jeff Law
2024-02-27 22:56 ` 钟居哲
0 siblings, 1 reply; 10+ messages in thread
From: Jeff Law @ 2024-02-27 15:22 UTC (permalink / raw)
To: juzhe.zhong, Robin Dapp, Edwin Lu, gcc-patches; +Cc: gnu-toolchain, pan2.li
On 2/26/24 18:21, juzhe.zhong@rivai.ai wrote:
> If the scheduling model increases the vsetvls, we shouldn't set it as
> default scheduling model
I don't think it's that simple. On some uarchs vsetvls are nearly free
while on others they can be fairly expensive. It's not clear (to me)
yet if one approach or the other is going to be the more common.
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-27 15:22 ` Jeff Law
@ 2024-02-27 22:56 ` 钟居哲
2024-02-27 23:53 ` Jeff Law
0 siblings, 1 reply; 10+ messages in thread
From: 钟居哲 @ 2024-02-27 22:56 UTC (permalink / raw)
To: Jeff Law, rdapp.gcc, ewlu, gcc-patches; +Cc: gnu-toolchain, pan2.li
[-- Attachment #1: Type: text/plain, Size: 1053 bytes --]
>> I don't think it's that simple. On some uarchs vsetvls are nearly free
>>while on others they can be fairly expensive. It's not clear (to me)
>>yet if one approach or the other is going to be the more common.
That's uarch dependent which is not the stuff I am talking about.
What's I want to say is that this patch breaks those testcases I added for VSETVL PASS testing.
And those testcases are uarch independent.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2024-02-27 23:22
To: juzhe.zhong@rivai.ai; Robin Dapp; Edwin Lu; gcc-patches
CC: gnu-toolchain; pan2.li
Subject: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
On 2/26/24 18:21, juzhe.zhong@rivai.ai wrote:
> If the scheduling model increases the vsetvls, we shouldn't set it as
> default scheduling model
I don't think it's that simple. On some uarchs vsetvls are nearly free
while on others they can be fairly expensive. It's not clear (to me)
yet if one approach or the other is going to be the more common.
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-27 22:56 ` 钟居哲
@ 2024-02-27 23:53 ` Jeff Law
2024-02-28 0:55 ` Palmer Dabbelt
0 siblings, 1 reply; 10+ messages in thread
From: Jeff Law @ 2024-02-27 23:53 UTC (permalink / raw)
To: 钟居哲, rdapp.gcc, ewlu, gcc-patches
Cc: gnu-toolchain, pan2.li
On 2/27/24 15:56, 钟居哲 wrote:
> >> I don't think it's that simple. On some uarchs vsetvls are nearly free
>>>while on others they can be fairly expensive. It's not clear (to me)
>>>yet if one approach or the other is going to be the more common.
>
> That's uarch dependent which is not the stuff I am talking about.
> What's I want to say is that this patch breaks those testcases I added
> for VSETVL PASS testing.
> And those testcases are uarch independent.
No, uarch impacts things like latency, which in turn impacts scheduling,
which in turn impacts vsetvl generation/optimization.
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-27 23:53 ` Jeff Law
@ 2024-02-28 0:55 ` Palmer Dabbelt
2024-02-28 9:18 ` juzhe.zhong
0 siblings, 1 reply; 10+ messages in thread
From: Palmer Dabbelt @ 2024-02-28 0:55 UTC (permalink / raw)
To: jeffreyalaw
Cc: juzhe.zhong, Robin Dapp, ewlu, gcc-patches, gnu-toolchain, pan2.li
On Tue, 27 Feb 2024 15:53:19 PST (-0800), jeffreyalaw@gmail.com wrote:
>
>
> On 2/27/24 15:56, 钟居哲 wrote:
>> >> I don't think it's that simple. On some uarchs vsetvls are nearly free
>>>>while on others they can be fairly expensive. It's not clear (to me)
>>>>yet if one approach or the other is going to be the more common.
>>
>> That's uarch dependent which is not the stuff I am talking about.
>> What's I want to say is that this patch breaks those testcases I added
>> for VSETVL PASS testing.
>> And those testcases are uarch independent.
> No, uarch impacts things like latency, which in turn impacts scheduling,
> which in turn impacts vsetvl generation/optimization.
Ya, and I think that's just what's expected for this sort of approach.
Edwin and I were working through that possibility in the office earlier,
but we didn't have the code up. So I figured I'd just go through one in
more detail to see if what we were talking about was sane. Grabbing
some arbitrary function in the changed set:
void
test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
vbool1_t v1 = *(vbool1_t*)in;
vbool64_t v2 = *(vbool64_t*)in;
*(vbool1_t*)(out + 100) = v1;
*(vbool64_t*)(out + 200) = v2;
}
we currently get (from generic-ooo)
test_vbool1_then_vbool64:
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
addi a3,a1,100
vsetvli a4,zero,e8,m8,ta,ma
addi a1,a1,200
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vsm.v v1,0(a1)
ret
but we could generate correct code with 2, 3, or 4 vsetvli instructions
depending on how things are scheduled. For example, with
-fno-schedule-insns I happen to get 3
test_vbool1_then_vbool64:
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
addi a3,a1,100
addi a1,a1,200
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vsm.v v1,0(a1)
ret
because the load/store with the same vcfg end up scheduled back-to-back.
I don't see any reason why something along the lines of
test_vbool1_then_vbool64:
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
addi a3,a1,100
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
addi a1,a1,200
vsm.v v1,0(a1)
ret
wouldn't be correct (though I just reordered the loads/stores and then
removed the redundant vsetvlis, so I might have some address calculation
wrong in there). The validity of removing a vsetvli depends on how the
dependant instructions get scheduled, which is very much under the
control of the pipeline model -- it's entirely possible the code with
more vsetvlis is faster, if vsetvli is cheap and scheduling ends up
hiding latency better.
So IMO it's completely reasonable to have vsetvli count ranges for a
test like this. I haven't looked at the others in any detail, but I
remember seeing similar things elsewhere last time I was poking around
these tests. We should probably double-check all these and write some
comments, just to make sure we're not missing any bugs, but I'd bet
there's a bunch of valid testsuite changes.
Like we talked about in the call this morning we should probably make
the tests more precise, but that's a larger effort. After working
through this I'm thinking it's a bit higher priority, though, as in this
case the bounds are so wide we're not even really testing the pass any
more.
>
> jeff
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-28 0:55 ` Palmer Dabbelt
@ 2024-02-28 9:18 ` juzhe.zhong
2024-02-28 10:24 ` Robin Dapp
0 siblings, 1 reply; 10+ messages in thread
From: juzhe.zhong @ 2024-02-28 9:18 UTC (permalink / raw)
To: palmer, jeffreyalaw
Cc: Robin Dapp, Edwin Lu, gcc-patches, gnu-toolchain, pan2.li
[-- Attachment #1: Type: text/plain, Size: 4267 bytes --]
I suggest specify -fno-schedule-insns to force tests assembler never change for any scheduling model.
juzhe.zhong@rivai.ai
From: Palmer Dabbelt
Date: 2024-02-28 08:55
To: jeffreyalaw
CC: juzhe.zhong; Robin Dapp; ewlu; gcc-patches; gnu-toolchain; pan2.li
Subject: Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
On Tue, 27 Feb 2024 15:53:19 PST (-0800), jeffreyalaw@gmail.com wrote:
>
>
> On 2/27/24 15:56, 钟居哲 wrote:
>> >> I don't think it's that simple. On some uarchs vsetvls are nearly free
>>>>while on others they can be fairly expensive. It's not clear (to me)
>>>>yet if one approach or the other is going to be the more common.
>>
>> That's uarch dependent which is not the stuff I am talking about.
>> What's I want to say is that this patch breaks those testcases I added
>> for VSETVL PASS testing.
>> And those testcases are uarch independent.
> No, uarch impacts things like latency, which in turn impacts scheduling,
> which in turn impacts vsetvl generation/optimization.
Ya, and I think that's just what's expected for this sort of approach.
Edwin and I were working through that possibility in the office earlier,
but we didn't have the code up. So I figured I'd just go through one in
more detail to see if what we were talking about was sane. Grabbing
some arbitrary function in the changed set:
void
test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
vbool1_t v1 = *(vbool1_t*)in;
vbool64_t v2 = *(vbool64_t*)in;
*(vbool1_t*)(out + 100) = v1;
*(vbool64_t*)(out + 200) = v2;
}
we currently get (from generic-ooo)
test_vbool1_then_vbool64:
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
addi a3,a1,100
vsetvli a4,zero,e8,m8,ta,ma
addi a1,a1,200
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vsm.v v1,0(a1)
ret
but we could generate correct code with 2, 3, or 4 vsetvli instructions
depending on how things are scheduled. For example, with
-fno-schedule-insns I happen to get 3
test_vbool1_then_vbool64:
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
addi a3,a1,100
addi a1,a1,200
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vsm.v v1,0(a1)
ret
because the load/store with the same vcfg end up scheduled back-to-back.
I don't see any reason why something along the lines of
test_vbool1_then_vbool64:
vsetvli a4,zero,e8,m8,ta,ma
vlm.v v2,0(a0)
addi a3,a1,100
vsm.v v2,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v1,0(a0)
addi a1,a1,200
vsm.v v1,0(a1)
ret
wouldn't be correct (though I just reordered the loads/stores and then
removed the redundant vsetvlis, so I might have some address calculation
wrong in there). The validity of removing a vsetvli depends on how the
dependant instructions get scheduled, which is very much under the
control of the pipeline model -- it's entirely possible the code with
more vsetvlis is faster, if vsetvli is cheap and scheduling ends up
hiding latency better.
So IMO it's completely reasonable to have vsetvli count ranges for a
test like this. I haven't looked at the others in any detail, but I
remember seeing similar things elsewhere last time I was poking around
these tests. We should probably double-check all these and write some
comments, just to make sure we're not missing any bugs, but I'd bet
there's a bunch of valid testsuite changes.
Like we talked about in the call this morning we should probably make
the tests more precise, but that's a larger effort. After working
through this I'm thinking it's a bit higher priority, though, as in this
case the bounds are so wide we're not even really testing the pass any
more.
>
> jeff
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-28 9:18 ` juzhe.zhong
@ 2024-02-28 10:24 ` Robin Dapp
2024-02-29 15:40 ` Palmer Dabbelt
0 siblings, 1 reply; 10+ messages in thread
From: Robin Dapp @ 2024-02-28 10:24 UTC (permalink / raw)
To: juzhe.zhong, palmer, jeffreyalaw
Cc: rdapp.gcc, Edwin Lu, gcc-patches, gnu-toolchain, pan2.li
> I suggest specify -fno-schedule-insns to force tests assembler never
> change for any scheduling model.
We already do that and that's the point - as I mentioned before, no
scheduling is worse than default scheduling here (for some definition
of worse). The way to reduce the number of vsetvls is to set the
load latency to a low value.
Regards
Robin
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] RISC-V: Update test expectancies with recent scheduler change
2024-02-28 10:24 ` Robin Dapp
@ 2024-02-29 15:40 ` Palmer Dabbelt
0 siblings, 0 replies; 10+ messages in thread
From: Palmer Dabbelt @ 2024-02-29 15:40 UTC (permalink / raw)
To: Robin Dapp
Cc: juzhe.zhong, jeffreyalaw, Robin Dapp, ewlu, gcc-patches,
gnu-toolchain, pan2.li
On Wed, 28 Feb 2024 02:24:40 PST (-0800), Robin Dapp wrote:
>> I suggest specify -fno-schedule-insns to force tests assembler never
>> change for any scheduling model.
>
> We already do that and that's the point - as I mentioned before, no
> scheduling is worse than default scheduling here (for some definition
> of worse). The way to reduce the number of vsetvls is to set the
> load latency to a low value.
I think -fno-schedule-insns is a perfectly reasonable way to get rid of
the test failures in the short term.
Using -fno-schedule-insns doesn't really fix the core fragility of the
tests, though: what the pass does depends very much on the order of
instructions it sees, so anything that reorders RTL is going to cause
churn in the tests. Sure getting rid of scheduling will get rid of a
big cause for reordering, but any pass could reorder RTL and thus change
the expected vsetvl counts.
Maybe the right thing to do here is to rewrite these as RTL tests? That
way we can very tightly control the input ordering. It's kind of the
opposite of Jeff's suggestion to add more debug output to the pass, but
I think that wouldn't actually solve the issue: we're not having trouble
matching assembly, the fragility comes from the input side.
That might be a "grass is always greener" thing, though, as I don't
think I've managed to write a useful RTL test yet...
>
> Regards
> Robin
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-02-29 15:40 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-23 23:10 [PATCH] RISC-V: Update test expectancies with recent scheduler change Edwin Lu
2024-02-26 13:29 ` Robin Dapp
2024-02-27 1:21 ` juzhe.zhong
2024-02-27 15:22 ` Jeff Law
2024-02-27 22:56 ` 钟居哲
2024-02-27 23:53 ` Jeff Law
2024-02-28 0:55 ` Palmer Dabbelt
2024-02-28 9:18 ` juzhe.zhong
2024-02-28 10:24 ` Robin Dapp
2024-02-29 15:40 ` Palmer Dabbelt
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