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To: chenxiaolong , gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn References: <20240105060522.26253-1-chenxiaolong@loongson.cn> From: chenglulu Message-ID: <2f42f90e-8e67-db6a-b60f-619ff9b9e9c0@loongson.cn> Date: Fri, 5 Jan 2024 20:30:12 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20240105060522.26253-1-chenxiaolong@loongson.cn> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8DxG95U9pdl8HADAA--.9042S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoWfCFykWF1fuw4DWFykur4Dtrc_yoW5Aw47Zo WjgFyY9r4Iq34ftrySkw12qryUWrn7Xrs5ZF47CrZ7CF9xXrs5AFW5Wr1vyFy7Ja13XFWk JFZ7WF4kCFyxtF47l-sFpf9Il3svdjkaLaAFLSUrUUUUbb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYI7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcVAKI48JMxk0xIA0c2IEe2 xFo4CEbIxvr21l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAq x4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r 1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF 7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxV W8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU wMKuUUUUU X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: pushed to r14-6954. ÔÚ 2024/1/5 ÏÂÎç2:05, chenxiaolong дµÀ: > - Change the default vectorization "-mlasx" option to "-mlsx" because there > are many non-aligned memory accesses when using 256-bit vectorization. > > - The following detection procedure is added to the target-supports.exp file: > > 1.check_effective_target_scalar_all_fma > 2.check_effective_target_vect_int > 3.check_effective_target_vect_intfloat_cvt > 4.check_effective_target_vect_doubleint_cvt > 5.check_effective_target_vect_intdouble_cvt > 6.check_effective_target_vect_uintfloat_cvt > 7.check_effective_target_vect_floatint_cvt > 8.check_effective_target_vect_floatuint_cvt > 9.check_effective_target_vect_shift > 10.check_effective_target_vect_var_shift > 11.check_effective_target_whole_vector_shift > 12.check_effective_target_vect_bswap > 13.check_effective_target_vect_bool_cmp > 14.check_effective_target_vect_char_add > 15.check_effective_target_vect_shift_char > 16.check_effective_target_vect_long > 17.check_effective_target_vect_float > 18.check_effective_target_vect_double > 19.check_effective_target_vect_long_long > 20.check_effective_target_vect_perm > 21.check_effective_target_vect_perm_byte > 22.check_effective_target_vect_perm_short > 23.check_effective_target_vect_widen_sum_hi_to_si > 24.check_effective_target_vect_widen_sum_qi_to_hi > 25.check_effective_target_vect_widen_sum_qi_to_hi > 26.check_effective_target_vect_widen_mult_qi_to_hi > 27.check_effective_target_vect_widen_mult_hi_to_si > 28.check_effective_target_vect_widen_mult_qi_to_hi_pattern > 29.check_effective_target_vect_widen_mult_hi_to_si_pattern > 30.check_effective_target_vect_widen_mult_si_to_di_pattern > 31.check_effective_target_vect_sdot_qi > 32.check_effective_target_vect_udot_qi > 33.check_effective_target_vect_sdot_hi > 34.check_effective_target_vect_udot_hi > 35.check_effective_target_vect_usad_char > 36.check_effective_target_vect_avg_qi > 37.check_effective_target_vect_pack_trunc > 38.check_effective_target_vect_unpack > 39.check_effective_target_vect_hw_misalign > 40.check_effective_target_vect_gather_load_ifn > 40.check_effective_target_vect_condition > 42.check_effective_target_vect_cond_mixed > 43.check_effective_target_vect_char_mult > 44.check_effective_target_vect_short_mult > 45.check_effective_target_vect_int_mult > 46.check_effective_target_vect_long_mult > 47.check_effective_target_vect_int_mod > 48.check_effective_target_vect_extract_even_odd > 49.check_effective_target_vect_interleave > 50.check_effective_target_vect_call_copysignf > 51.check_effective_target_vect_call_sqrtf > 52.check_effective_target_vect_call_lrint > 53.check_effective_target_vect_call_btrunc > 54.check_effective_target_vect_call_btruncf > 55.check_effective_target_vect_call_ceil > 56.check_effective_target_vect_call_ceilf > 57.check_effective_target_vect_call_floor > 58.check_effective_target_vect_call_floorf > 59.check_effective_target_vect_call_lceil > 60.check_effective_target_vect_call_lfloor > 61.check_effective_target_vect_logical_reduc > 62.check_effective_target_section_anchors > 63.check_vect_support_and_set_flags > 64.check_effective_target_vect_max_reduc > 65.check_effective_target_loongarch_sx > 66.check_effective_target_loongarch_sx_hw > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp: Add LoongArch to the list of supported > targets. > --- > gcc/testsuite/lib/target-supports.exp | 217 +++++++++++++++++++------- > 1 file changed, 162 insertions(+), 55 deletions(-) > > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index 167e630f5a5..9addf35ade4 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -3815,7 +3815,11 @@ proc add_options_for_bfloat16 { flags } { > # (fma, fms, fnma, and fnms) for both float and double. > > proc check_effective_target_scalar_all_fma { } { > - return [istarget aarch64*-*-*] > + if { [istarget aarch64*-*-*] > + || [istarget loongarch*-*-*]} { > + return 1 > + } > + return 0 > } > > # Return 1 if the target supports compiling fixed-point, > @@ -4051,6 +4055,8 @@ proc check_effective_target_vect_int { } { > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) > }}] > } > > @@ -4218,7 +4224,9 @@ proc check_effective_target_vect_intfloat_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vxe2]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports signed double->int conversion > @@ -4239,7 +4247,9 @@ proc check_effective_target_vect_doubleint_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports signed int->double conversion > @@ -4260,7 +4270,9 @@ proc check_effective_target_vect_intdouble_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > #Return 1 if we're supporting __int128 for target, 0 otherwise. > @@ -4293,7 +4305,9 @@ proc check_effective_target_vect_uintfloat_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vxe2]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > > @@ -4312,7 +4326,9 @@ proc check_effective_target_vect_floatint_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vxe2]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports unsigned float->int conversion > @@ -4329,7 +4345,9 @@ proc check_effective_target_vect_floatuint_cvt { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vxe2]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector integer char -> long long extend optab > @@ -4338,7 +4356,9 @@ proc check_effective_target_vect_floatuint_cvt { } { > proc check_effective_target_vect_ext_char_longlong { } { > return [check_cached_effective_target_indexed vect_ext_char_longlong { > expr { ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if peeling for alignment might be profitable on the target > @@ -7462,7 +7482,9 @@ proc check_effective_target_vect_shift { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports hardware vector shift by register operation. > @@ -7474,6 +7496,8 @@ proc check_effective_target_vect_var_shift { } { > || [istarget aarch64*-*-*] > || ([istarget riscv*-*-*] > && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) > }}] > } > > @@ -7490,7 +7514,9 @@ proc check_effective_target_whole_vector_shift { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) } { > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) } { > set answer 1 > } else { > set answer 0 > @@ -7507,6 +7533,7 @@ proc check_effective_target_vect_bswap { } { > expr { ([istarget aarch64*-*-*] > || [is-effective-target arm_neon] > || [istarget amdgcn-*-*]) > + || [istarget loongarch*-*-*] > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) }}] > } > @@ -7520,7 +7547,9 @@ proc check_effective_target_vect_bool_cmp { } { > || [istarget aarch64*-*-*] > || [is-effective-target arm_neon] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports addition of char vectors for at least > @@ -7543,6 +7572,8 @@ proc check_effective_target_vect_char_add { } { > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) > }}] > } > > @@ -7559,7 +7590,9 @@ proc check_effective_target_vect_shift_char { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports hardware vectors of long, 0 otherwise. > @@ -7580,7 +7613,9 @@ proc check_effective_target_vect_long { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) } { > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) } { > set answer 1 > } else { > set answer 0 > @@ -7610,7 +7645,9 @@ proc check_effective_target_vect_float { } { > && [check_effective_target_s390_vxe]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports hardware vectors of float without > @@ -7641,7 +7678,9 @@ proc check_effective_target_vect_double { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v])} }] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports conditional addition, subtraction, > @@ -7669,7 +7708,9 @@ proc check_effective_target_vect_long_long { } { > && [check_effective_target_has_arch_pwr8]) > || [istarget aarch64*-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v])}}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx])}}] > } > > > @@ -7724,7 +7765,9 @@ proc check_effective_target_vect_perm { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if, for some VF: > @@ -7819,7 +7862,9 @@ proc check_effective_target_vect_perm_byte { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports SLP permutation of 3 vectors when each > @@ -7850,7 +7895,9 @@ proc check_effective_target_vect_perm_short { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports SLP permutation of 3 vectors when each > @@ -7898,6 +7945,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } { > expr { [check_effective_target_vect_unpack] > || [istarget powerpc*-*-*] > || [istarget ia64-*-*] > + || [istarget loongarch*-*-*] > || [istarget riscv*-*-*] }}] > } > > @@ -7913,7 +7961,8 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { > expr { [check_effective_target_vect_unpack] > || [is-effective-target arm_neon] > || [istarget ia64-*-*] > - || [istarget riscv*-*-*] }}] > + || [istarget riscv*-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -7924,6 +7973,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } { > proc check_effective_target_vect_widen_sum_qi_to_si { } { > return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si { > expr { [istarget powerpc*-*-*] > + || [istarget loongarch*-*-*] > || [istarget riscv*-*-*] }}] > } > > @@ -7944,6 +7994,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { > || ([istarget aarch64*-*-*] > && ![check_effective_target_aarch64_sve]) > || [is-effective-target arm_neon] > + || [is-effective-target loongarch*-*-*] > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx])) > || [istarget amdgcn-*-*] }}] > @@ -7968,6 +8019,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { > && ![check_effective_target_aarch64_sve]) > || [istarget i?86-*-*] || [istarget x86_64-*-*] > || [is-effective-target arm_neon] > + || [is-effective-target loongarch*-*-*] > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx])) > || [istarget amdgcn-*-*] }}] > @@ -7985,6 +8037,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } { > && [check_effective_target_arm_little_endian]) > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > + || [istarget loongarch*-*-*] > || [istarget amdgcn-*-*] }}] > } > > @@ -7997,6 +8050,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } { > return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern { > expr { [istarget powerpc*-*-*] > || [istarget ia64-*-*] > + || [istarget loongarch*-*-*] > || [istarget i?86-*-*] || [istarget x86_64-*-*] > || ([is-effective-target arm_neon] > && [check_effective_target_arm_little_endian]) > @@ -8014,6 +8068,7 @@ proc check_effective_target_vect_widen_mult_si_to_di_pattern { } { > return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern { > expr { [istarget ia64-*-*] > || [istarget i?86-*-*] || [istarget x86_64-*-*] > + || [istarget loongarch*-*-*] > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) }}] > } > @@ -8041,7 +8096,9 @@ proc check_effective_target_vect_sdot_qi { } { > || ([istarget mips*-*-*] > && [et-is-effective-target mips_msa]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -8058,7 +8115,9 @@ proc check_effective_target_vect_udot_qi { } { > || ([istarget mips*-*-*] > && [et-is-effective-target mips_msa]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -8087,7 +8146,9 @@ proc check_effective_target_vect_sdot_hi { } { > || ([istarget mips*-*-*] > && [et-is-effective-target mips_msa]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -8101,7 +8162,9 @@ proc check_effective_target_vect_udot_hi { } { > || ([istarget mips*-*-*] > && [et-is-effective-target mips_msa]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -8118,7 +8181,9 @@ proc check_effective_target_vect_usad_char { } { > || ([istarget powerpc*-*-*] > && [check_p9vector_hw_available]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports both signed > @@ -8128,7 +8193,9 @@ proc check_effective_target_vect_avg_qi {} { > return [expr { ([istarget aarch64*-*-*] > && ![check_effective_target_aarch64_sve1_only]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }] > } > > # Return 1 if the target plus current options supports both signed > @@ -8167,7 +8234,9 @@ proc check_effective_target_vect_pack_trunc { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn*-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options supports a vector > @@ -8189,7 +8258,9 @@ proc check_effective_target_vect_unpack { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn*-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target plus current options does not guarantee > @@ -8230,7 +8301,8 @@ proc check_effective_target_vect_hw_misalign { } { > || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > - || ([istarget riscv*-*-*]) } { > + || ([istarget riscv*-*-*]) > + || ([istarget loongarch*-*-*]) } { > return 1 > } > if { [istarget arm*-*-*] > @@ -8849,7 +8921,8 @@ proc check_effective_target_vect_gather_load_ifn { } { > proc check_effective_target_vect_scatter_store { } { > return [expr { [check_effective_target_aarch64_sve] > || [istarget amdgcn*-*-*] > - || [check_effective_target_riscv_v] }] > + || [check_effective_target_riscv_v] > + || [check_effective_target_loongarch_sx] }] > } > > # Return 1 if the target supports vector conditional operations, 0 otherwise. > @@ -8868,7 +8941,9 @@ proc check_effective_target_vect_condition { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector conditional operations where > @@ -8887,7 +8962,9 @@ proc check_effective_target_vect_cond_mixed { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector char multiplication, 0 otherwise. > @@ -8905,7 +8982,9 @@ proc check_effective_target_vect_char_mult { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector short multiplication, 0 otherwise. > @@ -8924,7 +9003,9 @@ proc check_effective_target_vect_short_mult { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector int multiplication, 0 otherwise. > @@ -8942,7 +9023,9 @@ proc check_effective_target_vect_int_mult { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports 64 bit hardware vector > @@ -8961,7 +9044,9 @@ proc check_effective_target_vect_long_mult { } { > || ([istarget mips*-*-*] > && [et-is-effective-target mips_msa]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) } { > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) } { > set answer 1 > } else { > set answer 0 > @@ -8999,7 +9084,9 @@ proc check_effective_target_vect_extract_even_odd { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector interleaving, 0 otherwise. > @@ -9017,7 +9104,9 @@ proc check_effective_target_vect_interleave { } { > || ([istarget s390*-*-*] > && [check_effective_target_s390_vx]) > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > foreach N {2 3 4 5 6 7 8} { > @@ -9142,7 +9231,9 @@ proc check_effective_target_vect_call_copysignf { } { > || [istarget aarch64*-*-*] > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports hardware square root instructions. > @@ -9181,7 +9272,9 @@ proc check_effective_target_vect_call_sqrtf { } { > && [check_effective_target_s390_vx]) > || [istarget amdgcn-*-*] > || ([istarget riscv*-*-*] > - && [check_effective_target_riscv_v]) }}] > + && [check_effective_target_riscv_v]) > + || ([istarget loongarch*-*-*] > + && [check_effective_target_loongarch_sx]) }}] > } > > # Return 1 if the target supports vector lrint calls. > @@ -9190,7 +9283,8 @@ proc check_effective_target_vect_call_lrint { } { > set et_vect_call_lrint 0 > if { (([istarget i?86-*-*] || [istarget x86_64-*-*]) > && [check_effective_target_ilp32]) > - || [istarget amdgcn-*-*] } { > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] } { > set et_vect_call_lrint 1 > } > > @@ -9203,7 +9297,8 @@ proc check_effective_target_vect_call_lrint { } { > proc check_effective_target_vect_call_btrunc { } { > return [check_cached_effective_target_indexed vect_call_btrunc { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector btruncf calls. > @@ -9211,7 +9306,8 @@ proc check_effective_target_vect_call_btrunc { } { > proc check_effective_target_vect_call_btruncf { } { > return [check_cached_effective_target_indexed vect_call_btruncf { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector ceil calls. > @@ -9219,7 +9315,8 @@ proc check_effective_target_vect_call_btruncf { } { > proc check_effective_target_vect_call_ceil { } { > return [check_cached_effective_target_indexed vect_call_ceil { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector ceilf calls. > @@ -9227,7 +9324,8 @@ proc check_effective_target_vect_call_ceil { } { > proc check_effective_target_vect_call_ceilf { } { > return [check_cached_effective_target_indexed vect_call_ceilf { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector floor calls. > @@ -9235,7 +9333,8 @@ proc check_effective_target_vect_call_ceilf { } { > proc check_effective_target_vect_call_floor { } { > return [check_cached_effective_target_indexed vect_call_floor { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector floorf calls. > @@ -9243,21 +9342,24 @@ proc check_effective_target_vect_call_floor { } { > proc check_effective_target_vect_call_floorf { } { > return [check_cached_effective_target_indexed vect_call_floorf { > expr { [istarget aarch64*-*-*] > - || [istarget amdgcn-*-*] }}] > + || [istarget amdgcn-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector lceil calls. > > proc check_effective_target_vect_call_lceil { } { > return [check_cached_effective_target_indexed vect_call_lceil { > - expr { [istarget aarch64*-*-*] }}] > + expr { [istarget aarch64*-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector lfloor calls. > > proc check_effective_target_vect_call_lfloor { } { > return [check_cached_effective_target_indexed vect_call_lfloor { > - expr { [istarget aarch64*-*-*] }}] > + expr { [istarget aarch64*-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports vector nearbyint calls. > @@ -9294,6 +9396,7 @@ proc check_effective_target_vect_logical_reduc { } { > return [expr { [check_effective_target_aarch64_sve] > || [istarget amdgcn-*-*] > || [check_effective_target_riscv_v] > + || [check_effective_target_loongarch_sx] > || [istarget i?86-*-*] || [istarget x86_64-*-*]}] > } > > @@ -9311,7 +9414,8 @@ proc check_effective_target_section_anchors { } { > return [check_cached_effective_target section_anchors { > expr { [istarget powerpc*-*-*] > || [istarget arm*-*-*] > - || [istarget aarch64*-*-*] }}] > + || [istarget aarch64*-*-*] > + || [istarget loongarch*-*-*] }}] > } > > # Return 1 if the target supports atomic operations on "int_128" values. > @@ -11623,8 +11727,10 @@ proc check_vect_support_and_set_flags { } { > set dg-do-what-default compile > } > } elseif [istarget loongarch*-*-*] { > - lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlasx" > - if [check_effective_target_loongarch_asx_hw] { > + # Set the default vectorization option to "-mlsx" due to the problem > + # of non-aligned memory access when using 256-bit vectorization. > + lappend DEFAULT_VECTCFLAGS "-mdouble-float" "-mlsx" > + if [check_effective_target_loongarch_sx_hw] { > set dg-do-what-default run > } else { > set dg-do-what-default compile > @@ -12190,7 +12296,8 @@ proc check_effective_target_builtin_eh_return { } { > > proc check_effective_target_vect_max_reduc { } { > if { [istarget aarch64*-*-*] || [is-effective-target arm_neon] > - || [check_effective_target_riscv_v] } { > + || [check_effective_target_riscv_v] > + || [check_effective_target_loongarch_sx] } { > return 1 > } > return 0 > @@ -13205,7 +13312,7 @@ proc check_effective_target_loongarch_sx { } { > #if !defined(__loongarch_sx) > #error "LSX not defined" > #endif > - }] > + } "-mlsx"] > } > > proc check_effective_target_loongarch_sx_hw { } { > @@ -13225,7 +13332,7 @@ proc check_effective_target_loongarch_asx { } { > #if !defined(__loongarch_asx) > #error "LASX not defined" > #endif > - }] > + } "-mlasx"] > } > > proc check_effective_target_loongarch_asx_hw { } {