Re: [PATCH] RISC-V: Fix SEW64 of vrsub.vx runtime fail in RV32 system

[Jeff Law <jeffreyalaw@gmail.com>]

On 4/2/23 18:38, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> It's quite obvious that the order of vrsub SEW64 is wrong.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Fix incorrect operand order.
Note the formatting in that code is wrong on multiple levels.  While I 
don't typically get nit-picky on formatting, this needs serious cleanup 
for gcc-14:

>  if (riscv_vector::sew64_scalar_helper (
>     operands,
>     /* scalar op */&operands[3],
>     /* vl */operands[5],
>     <MODE>mode,
>     <VM>mode,                      
>     riscv_vector::simm5_p (operands[3]),
>     [] (rtx *operands, rtx boardcast_scalar) {
>       emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
>            operands[2], boardcast_scalar, operands[4], operands[5],
>            operands[6], operands[7]));
>         }))


Please review the coding standards, particularly with regards to 
indention and function call parameters.  When you find that you're 
writing code like this:

   emit_insn (gen_something (x, y,
    x, p, q, r, s, t));

Please break it up.   Pull the generator call out and store its result 
in a temporary.  Then fix the indention of its arguments so that it 
looks like this:

   temp = gen_something (some_long_argument, another_long_argument,
                         more_long_args, something_else);


The coding standards exist to make it easier for everyone to be able to 
understand your code without having to waste mental energy parsing 
different formatting styles.

As it stands I'm spending *far* too much mental energy just trying to 
figure out what arguments are associated with what calls.  That's just 
crazy.

jeff