From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id B75A83858CDA for ; Fri, 28 Jul 2023 16:40:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B75A83858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-686f090310dso2158670b3a.0 for ; Fri, 28 Jul 2023 09:40:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690562435; x=1691167235; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=nywTkoGMU2fST3G5umtaqdaVH7jtQ4diF7q3RV7wVyE=; b=N1LplfQsvRpTVUHE4FykPkUAp09qeZP5mNGhzN3UZL4OPYtCTS8HvNrydq/12Xn+wh nQR3nv9gONudl8Q9rzbWlJ64UvjCIIT5izK9KpckkiYZgQu/jY/57I7XChqKYs2dkh6D ap5I5hVtnJ1OAMXAKiRvRd6eKuX/+O5xHh36JhhsvUhIpYAhDu0bGBwvpzAkt2diXRcz zLySDbee0bdxConc1KYsLkWS/8OvTbGP1Bqu/V14mJvoMOrNM+cucH2dJHjhunkAUuad 1b39R8xfIB0+3E65zQP1ubtfU2L0RJMBuIiYoQyKV0PSi/E0KBM8P625jVUxaBOyftwQ QY9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690562435; x=1691167235; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nywTkoGMU2fST3G5umtaqdaVH7jtQ4diF7q3RV7wVyE=; b=WMqwSqshsaqdM1xWm4sZrPgcOnsu9nKTh+uhY/iHHwlwwDCoCrF5rT+tnTu8dx377A Cj8W2Cqj98MJNf75+jYZS3p5rWx6ZgF2THUOq4AbGL6Vw5PCJqQgZDwDVmms8H776IUJ AbLOUuOzFkwwI3lLa9cFrDh5GejLEM6n25gkHexjmPQS/Sng7lI3UpWkEOOMAIKutmRY stFf2VKMvY5k3aO0s9h4Zde/cG7CAYXmcFz9+CLyxOzGnVNbxezoqVmtAKiNPzAb8jLQ uzdQP5/7DlxJESQ7hNeHbk/1ZrgicCoV3xvX7yq7JQ6A7xs4nDoghBKwbU3u9zQJ2fQW Yw7A== X-Gm-Message-State: ABy/qLZYVqWP92B1ZgFB0EaduNvA0pDc3bgqZbT2Nnf1d1KAghO18dL1 LBPpbbyf4zqPJsbqYLoX70ACEA== X-Google-Smtp-Source: APBJJlHQy/SJG4qb4nbgeTnApjk/efuGKUPuXm08A4it0E18s9UiQi7sqmzWrA+AsBmPQxADNZE/jw== X-Received: by 2002:a05:6300:8081:b0:133:7276:324b with SMTP id ap1-20020a056300808100b001337276324bmr2386162pzc.23.1690562435340; Fri, 28 Jul 2023 09:40:35 -0700 (PDT) Received: from [10.0.17.156] ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id f14-20020a63754e000000b0056399ef039esm3785413pgn.77.2023.07.28.09.40.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jul 2023 09:40:35 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------f3QyMftRN0LVkCPQ0y0y1A90" Message-ID: <30148603-3d23-ed51-a61c-291cfff1baaf@rivosinc.com> Date: Fri, 28 Jul 2023 09:40:33 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative Content-Language: en-US To: "juzhe.zhong" Cc: Kito Cheng , "demin.han" , gcc-patches References: <20230727094859.3884298-1-demin.han@starfivetech.com> <4F1CE7168EFB3E1A+2023072718223714228879@rivai.ai> <9819777D4BE5D5B8+4EB8A5B1-0546-4283-910B-CD4EA60B1F7A@rivai.ai> From: Patrick O'Neill In-Reply-To: <9819777D4BE5D5B8+4EB8A5B1-0546-4283-910B-CD4EA60B1F7A@rivai.ai> X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------f3QyMftRN0LVkCPQ0y0y1A90 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Thanks! Here's the comitted patch: https://inbox.sourceware.org/gcc-patches/20230728163758.377962-1-patrick@rivosinc.com/T/#u On 7/27/23 15:11, juzhe.zhong wrote: > LGTM.Thanks. You can go ahead commit it. > ---- Replied Message ---- > From Patrick O'Neill > Date 07/28/2023 04:46 > To Kito Cheng , > juzhe.zhong@rivai.ai > Cc demin.han > , > gcc-patches > Subject Re: [PATCH] RISC-V: Fix uninitialized and redundant use of > which_alternative > > The newly added testcase fails on rv32 targets with this message: > FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test for excess errors) > > verbose log: > compiler exited with status 1 > output is: > cc1: error: ABI requires '-march=rv32' > > Something like this appears to fix the issue: > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > index 14a9802667e..e10a9e9d0f5 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > @@ -1,5 +1,5 @@ >  /* { dg-do compile } */ > -/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ > +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 > -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" > } */ > >  long >  foo (long *__restrict a, long *__restrict b, long n) > > On 7/27/23 04:57, Kito Cheng via Gcc-patches wrote: >> My first impression is those emit_insn (gen_rtx_SET()) seems >> necessary, but I got the point after I checked vector.md :P >> >> Committed to trunk, thanks :) >> >> >> On Thu, Jul 27, 2023 at 6:23 PMjuzhe.zhong@rivai.ai >> wrote: >>> Oh, YES. >>> >>> Thanks for fixing it. It makes sense since the ternary operations in "vector.md" >>> generate "vmv.v.v" according to RA. >>> >>> Thanks for fixing it. >>> >>> @kito: Could you confirm it? If it's ok to you, commit it for Han (I am lazy to commit patches :). >>> >>> >>> >>> juzhe.zhong@rivai.ai >>> >>> From: demin.han >>> Date: 2023-07-27 17:48 >>> To:gcc-patches@gcc.gnu.org >>> CC:kito.cheng@gmail.com;juzhe.zhong@rivai.ai >>> Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative >>> When pass split2 starts, which_alternative is random depending on >>> last set of certain pass. >>> >>> Even initialized, the generated movement is redundant. >>> The movement can be generated by assembly output template. >>> >>> Signed-off-by: demin.han >>> >>> gcc/ChangeLog: >>> >>> * config/riscv/autovec.md: Delete which_alternative use in split >>> >>> gcc/testsuite/ChangeLog: >>> >>> * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test. >>> >>> --- >>> gcc/config/riscv/autovec.md | 12 ------------ >>> .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 13 +++++++++++++ >>> 2 files changed, 13 insertions(+), 12 deletions(-) >>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >>> >>> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md >>> index d899922586a..b7ea3101f5a 100644 >>> --- a/gcc/config/riscv/autovec.md >>> +++ b/gcc/config/riscv/autovec.md >>> @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms" >>> [(const_int 0)] >>> { >>> riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> - if (which_alternative == 2) >>> - emit_insn (gen_rtx_SET (operands[0], operands[3])); >>> rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; >>> riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, mode), >>> riscv_vector::RVV_TERNOP, ops, operands[4]); >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >>> new file mode 100644 >>> index 00000000000..14a9802667e >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >>> @@ -0,0 +1,13 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ >>> + >>> +long >>> +foo (long *__restrict a, long *__restrict b, long n) >>> +{ >>> + long i; >>> + for (i = 0; i < n; ++i) >>> + a[i] = b[i] + i * 8; >>> + return a[1]; >>> +} >>> + >>> +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */ >>> -- >>> 2.41.0 >>> >>> --------------f3QyMftRN0LVkCPQ0y0y1A90--